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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com XRT73L04B 4 channel ds3/e3/sts-1 line interface unit october 2003 rev. 1.0.1 general description the XRT73L04B, 4-channel, ds3/e3/sts-1 line in- terface unit is a low power cmos version of the xrt73l04a and consists of four independent line transmitters and receivers integrated on a single chip designed for ds3, e3 or sonet sts-1 applications. each channel of the XRT73L04B can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. each channel can be configured to operate in a mode/data rate that is independent of the other channels. in the transmit direction, each channel encodes input data to either b3zs (ds3/sts-1) or hdb3 (e3) for- mat and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. in the receive direction, the XRT73L04B performs equalization on incoming signals, performs clock re- covery, decodes data from either b3zs or hdb3 for- mat, converts the receive data into ttl/cmos for- mat, checks for los or lol conditions and detects and declares the occurrence of line code violations. features ? incorporates an improved timing recovery circuit and is pin and functional compatible to xrt73l04a ? meets e3/ds3/sts-1 jitter tolerance require- ments ? contains a 4-wire microprocessor serial interface ? full loop-back capability ? transmit and receive power down modes ? full redundancy support ? uses minimum external components ? single +3.3v power supply ? low power cmos design ? 5v tolerant i/o ? -40c to +85c operating temperature range ? available in a thermally enhanced 144 pin lqfp package applications ? digital cross connect systems ? csu/dsu equipment ? routers ? fiber optic terminals ? multiplexers ? atm switches f igure 1. XRT73L04B b lock d iagram rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) txlev_(n) txoff channel 2 agc/ equalizer serial processor interface peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr sdi sdo sclk cs/(sr/dr) regr rtip_(n) rring_(n) reqen_(n) channel 0 channel 1 notes: 1. (n) = 0, 1, 2 , or 3 for respective channels 2. serial processor interface input pins are shared by the four channels in host mode and redefined in hardware mode. device monitor mtip_(n) mring_(n) dmo_(n) transmit logic duty cycle adjust ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder e3_(n) sts-1/ds3_(n) host/(hw) rlol_(n) exclk_(n) rxoff rxclkinv rxclk_(n) rpos_(n) rneg_(n)/ (lcv_(n)) channel 3 tx control
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 2 typical applications transmit interface characteristics: ? accepts either single-rail or dual-rail data from terminal equipment and generates a bipolar signal from the line ? integrated pulse shaping circuit ? built-in b3zs/hdb3 encoder (which can be dis- abled) ? contains transmit clock duty cycle correction circuit on-chip ? generates pulses that comply with the itu-t g.703 pulse template (e3 applications) ? generates pulses that comply with the dsx-3 pulse template as specified in bellcore gr-499 -core and ansi t1.102_1993 ? generates pulses that comply with the stsx-1 pulse template as specified in bellcore gr-253- core ? transmitter can be turned off in order to support redundancy designs receive interface characteristics: ? integrated adaptive receive equalization (optional) and timing recovery ? declares and clears the los defect per itu-t g.775 requirements (e3 and ds3 applications) ? meets jitter tolerance requirements as specified in itu-t g.823_1993 (e3 applications) ? meets jitter tolerance requirements as specified in bellcore gr-499-core (ds3 applications) ? declares loss of signal (los) and loss of lock (lol) alarms ? built-in b3zs/hdb3 decoder (which can be dis- abled) ? recovered data can be muted while the los con- dition is declared ? outputs either single-rail or dual-rail data to the terminal equipment ? receiver can be powered down in order to con- serve power in redundancy designs f igure 2. m ulti c hannel atm a pplication atm switch/ sar xrt74l74 rpos rneg rxlineclk xrt71d04 XRT73L04B rrpos rrneg rrclk rpos rneg rxclk rpos rneg rxclk rtip rring ttip tring tpos tneg txlineclk mclk tpos tneg txclk 4 channel e3/ds3 atm uni 4 channel e3/ds3 j/a 4 channel e3/ds3 liu f igure 3. m ulti s ervice - f rame r elay a pplication frame relay xrt72l58 rpos rneg rxlineclk xrt71d04 XRT73L04B rrpos rrneg rrclk rpos rneg rxclk rpos rneg rxclk rtip rring ttip tring tpos tneg txlineclk mclk tpos tneg txclk 8 channel e3/ds3 framer 2 x 4 channel e3/ds3 j/a 2 x 4 channel e3/ds3 liu
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 3 ordering information f igure 4. p in out of the XRT73L04B in the 144 p in tqfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 XRT73L04B mring_2 mtip_2 ttip_2 txavdd_2 tring_2 txagnd_2 txclk_3 tpdata_3 tndata_3 txavdd_3 dmo_3 ttip_3 txavdd_3 tring_3 txagnd_3 mtip_3 mring_3 txagnd_3 txagnd_1 mring_1 mtip_1 txagnd_1 tring_1 txavdd_1 ttip_1 dmo_1 txavdd_1 tndata_1 tpdata_1 txclk_1 txagnd_0 tring_0 txavdd_0 ttip_0 mtip_0 mring_0 e3_2 e3_3 sts1/ds3_2 llb_2 rlb_2 rxavdd_2 rring_2 rtip_2 rxagnd_2 reqen_2 sts1/ds3_3 llb_3 rlb_3 rxavdd_3 rring_3 rtip_3 rxagnd_3 reqen_3 reqen_1 rxagnd_1 rtip_1 rring_1 rxavdd_1 rlb_1 llb_1 sts1/ds3_1 reqen_0 rxagnd_0 rtip_0 rring_0 rxavdd_0 rlb_0 llb_0 losthr ict sts1/ds3_0 agnd_2 regr/(rxclkinv) losmuten agnd_3 rlol_3 rlos_3 exclk_2 rlol_2 rlos_2 rxdgnd_2 rpos_2 rneg_2/lcv_2 rxclk_2 rxdvdd_2 exclk_3 rxdgnd_3 rpos_3 rneg3/lcv_3 rxclk_3 rxdvdd_3 exdgnda exdvdda txoff txagnd_2 dmo_2 txavdd_2 taos_2 taos_3 txlev_2 txlev_3 txclk_2 tpdata_2 tndata_2 nc nc nc sdo/e3_0 sdi/e3_1 sclk/(rxoff) cs/(sr/dr) rlol_1 rlos_1 exclk_0 rlol_0 rlos_0 agnd_1 rxdgnd_0 rpos_0 rneg_0/lcv_0 rxclk_0 rxdvdd_0 exclk_1 rxdgnd_1 rpos_1 rneg_1/lcv_1 rxclk_1 host/(hw) rxdvdd_1 agnd_0 txagnd_0 dmo_0 txavdd_0 taos_0 taos_1 txlev_0 txlev_1 txclk_0 tpdata_0 tndata_0 nc nc nc p art #p ackage o perating temperature r ange XRT73L04Biv 144 pin lqfp 20 x 20 x 1.4 mm -40 o c to +85 o c
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 i table of contents g eneral description ......................................................................................................... 1 f eatures .............................................................................................................................. ...................... 1 applications .................................................................................................................. ....................... 1 figure 1.XRT73L04B block diagram .............................................................................................. .................. 1 t ypical a pplications .............................................................................................................................. ... 2 figure 2.multichannel atm application ......................................................................................... ................... 2 figure 3.multiservice - frame relay application ............................................................................... ............... 2 t ransmit i nterface c haracteristics : ..................................................................................................... 2 r eceive i nterface c haracteristics : ....................................................................................................... 2 figure 4.pin out of the XRT73L04B in the 144 pin tqfp package ................................................................. . 3 o rdering information ....................................................................................................... 3 table of contents ....................................................................................................... i p in d escriptions ( by function ) ......................................................................................... 4 t ransmit i nterface .............................................................................................................................. ..... 4 r eceive i nterface .............................................................................................................................. ....... 6 c lock i nterface .............................................................................................................................. .......... 7 o perating m ode s elect ........................................................................................................................... 8 c ontrol and a larm i nterface ................................................................................................................. 9 m icroprocessor i nterface .................................................................................................................... 11 p ower and g round p ins ......................................................................................................................... 13 n o c onnection p ins .............................................................................................................................. .. 14 e lectrical characteristics ........................................................................................... 15 a bsolute m aximum r atings .................................................................................................................... 15 dc electrical characteristics ................................................................................................. ......... 15 ac electrical characteristics (see figure 5) ................................................................................... ..................... 16 terminal side timing parameters (see figure 6 and figure 7) -- {(n) = 0, 1, 2 or 3 } ......................................... 16 figure 5.transmit pulse amplitude test circuit for e3, ds3 and sts-1 rates (typical channel) .................. 17 figure 6.timing diagram of the transmit terminal input interface .............................................................. ... 17 figure 7.timing diagram of the receive terminal output interface .............................................................. . 17 line side parameters e3 application ........................................................................................... ........................ 18 transmit characteristics (see figure 5) ........................................................................................ ....................... 18 line side parameters sonet sts-1 application .................................................................................. ................. 19 transmit characteristics (see figure 5) ........................................................................................ ....................... 19 line side parameters ds3 application .......................................................................................... ...................... 20 transmit characteristics (see figure 5) ........................................................................................ ....................... 20 figure 8.itu-t g.703 transmit output pulse template for e3 applications .................................................. 21 figure 9.bellcore gr-499-core transmit output pulse template for ds3 applications ............................. 21 figure 10.bellcore gr-253-core transmit output pulse template for sonet sts-1 applications ........... 22 figure 11.microprocessor serial interface data structure ...................................................................... ........ 22 microprocessor serial interface timing (see figure 12) ......................................................................... ............. 23 figure 12.timing diagram for the microprocessor serial interface .............................................................. ... 23 system description .................................................................................................. 24 t he t ransmit s ection - c hannels 0, 1, 2, and 3 .................................................................................... 24 t he r eceive s ection - c hannels 0, 1, 2 and 3 ....................................................................................... 24 t he m icroprocessor s erial i nterface ................................................................................................. 24 table 1:role of microprocessor serial interface pins when the XRT73L04B is operating in the hardware mode 24 figure 13.functional block diagram of the XRT73L04B ........................................................................... ..... 25
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 ii 1.0 selecting the data rate ................................................................................................... ............ 25 1.1 c onfiguring c hannel ( n ) ............................................................................................................ 25 table 2:hexadecimal addresses and bit formats of XRT73L04B command registers ............................... 26 table 3:selecting the data rate for channel(n) via the e3_(n) and sts-1/ds3_(n) input pins (hardware mode) 27 c ommand r egister , cr4-( n ) ........................................................................................................... 27 table 4:selecting the data rate for channel(n) via the sts-1/ds3_(n) and the e3_(n) bit-fields within the ap- propriate command register (host mode) ..................................................................................... 27 2.0 the transmit section ...................................................................................................... ................ 28 2.1 t he t ransmit l ogic b lock ......................................................................................................... 28 accepting dual-rail data from the terminal equipment ................................................................... 28 figure 14. the typical interface for the transmission of data in a dual-rail format from the transmitting ter- minal equipment to the transmit section of a channel .................................................................... 28 figure 15.the XRT73L04B samples the data on the tpdata and tndata input pins ................................... 28 accepting single-rail data from the terminal equipment ................................................................ 29 c ommand r egister cr3-( n ) ............................................................................................................ 29 figure 16.the behavior of the tpdata and txclk input sgnals, while the transmit logic block is accepting sin- gle-rail data from the terminal equipment ..................................................................................... 29 2.2 t he t ransmit c lock d uty c ycle a djust c ircuitry ................................................................. 29 2.3 t he hdb3/b3zs e ncoder b lock ............................................................................................... 29 b3zs encoding ................................................................................................................. ................. 29 figure 17.an example of b3zs encoding ......................................................................................... ............. 30 hdb3 encoding ................................................................................................................. ................ 30 figure 18.an example of hdb3 encoding ......................................................................................... ............ 30 disabling the hdb3/b3zs encoder ............................................................................................... .... 30 c ommand r egister cr3-( n ) ............................................................................................................ 31 2.4 t he t ransmit p ulse s haping c ircuitry .................................................................................... 31 figure 19.the bellcore gr-499-core transmit output pulse template for ds3 applications .................... 31 figure 20.the bellcore gr-253-core transmit output pulse template for sonet sts-1 applications ... 32 enabling the transmit line build-out circuit .................................................................................. ... 32 c ommand r egister , cr1-( n ) ........................................................................................................... 32 disabling the transmit line build-out circuit ................................................................................. ... 32 c ommand r egister , cr1-( n ) ........................................................................................................... 33 design guideline for setting the transmit line build-out circuit ...................................................... 33 the transmit line build-out circuit and e3 applications .................................................................. 33 2.5 i nterfacing the t ransmit s ections of the XRT73L04B to the l ine ...................................... 33 figure 21.recommended schematic for interfacing the transmit section of the XRT73L04B to the line .... 33 t ransformer r ecommendations .................................................................................................... 34 3.0 the receive section ....................................................................................................... .................. 35 3.1 i nterfacing the r eceive s ections of the XRT73L04B to the l ine ........................................ 35 figure 22.recommended schematic for interfacing the receive section of the XRT73L04B to the line (trans- former-coupling) .............................................................................................................. ................ 35 3.2 t he r eceive e qualizer b lock ................................................................................................... 36 figure 23.the typical application for the system installer .................................................................... ........ 36 guidelines for setting the receive equalizer ................................................................................. .. 36
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 iii c ommand r egister cr-2( n ) ............................................................................................................ 37 3.3 c lock r ecovery pll .................................................................................................................. 38 the training mode ............................................................................................................. ................ 38 the data/clock recovery mode .................................................................................................. ...... 38 3.4 t he hdb3/b3zs d ecoder .......................................................................................................... 38 b3zs decoding (ds3/sts-1 applications) ........................................................................................ 38 figure 24.an example of b3zs decoding ......................................................................................... ............. 38 hdb3 decoding (e3 applications) ............................................................................................... ...... 38 figure 25.an example of hdb3 decoding ......................................................................................... ............. 39 configuring the hdb3/b3zs decoder ............................................................................................. ... 39 c ommand r egister cr3-( n ) ............................................................................................................ 39 3.5 los d eclaration /c learance ..................................................................................................... 39 the los declaration/clearance criteria for e3 applications ............................................................. 39 figure 26.the signal levels that the XRT73L04B declares and clears los ................................................. 40 figure 27.the behavior of the los output indicator in response to the loss of signal and the restoration of signal ........................................................................................................................ ........................ 41 the los declaration/clearance criteria for ds3 and sts-1 applications ........................................ 41 table 5:the alos (analog los) declare and clear thresholds for a given setting of losthr and reqen (ds3 and sts-1 applications) .................................................................................................. ......... 41 c ommand r egister cr0-( n ) ............................................................................................................ 42 c ommand r egister cr2-( n ) ............................................................................................................ 42 c ommand r egister cr0-( n ) ............................................................................................................ 42 c ommand r egister cr2-( n ) ............................................................................................................ 42 muting the recovered data while the los is being declared ........................................................... 42 c ommand r egister cr3-( n ) ............................................................................................................ 43 3.6 r outing the r ecovered t iming and d ata i nformation to the r eceiving t erminal e quipment . 43 routing dual-rail format data to the receiving terminal equipment .............................................. 43 figure 28.the typical interface for the transmission of data in a dual-rail format, from the receive section of the XRT73L04B to the receiving terminal equipment .................................................................... 43 figure 29.how the XRT73L04B outputs data on the rpos and rneg output pins ...................................... 44 figure 30.the behavior of the rpos, rneg, and rxclk signals when rxclk is inverted ............................. 44 c ommand r egister cr3-( n ) ............................................................................................................ 45 routing single-rail format (binary data stream) data to the receive terminal equipment ............ 45 c ommand r egister cr3-( n ) ............................................................................................................ 45 figure 31.the typical interface for the transmission of data in a single-rail format from the receive section of the XRT73L04B to the receiving terminal equipment ................................................................ 45 figure 32.the behavior of the rpos and rxclk output signals while the XRT73L04B is transmitting single-rail data to the receiving terminal equipment ...................................................................................... . 46 3.7 s hutting off the r eceive s ection ........................................................................................... 46 c ommand r egister cr3-( n ) ............................................................................................................ 46 4.0 diagnostic features of the XRT73L04B .................................................................................... 4 7 4.1 t he a nalog l ocal l oop -b ack m ode ......................................................................................... 47 figure 33. a channel operating in the analog local loop-back mode ........................................................... 4 7 4.2 t he d igital l ocal l oop -b ack m ode . ......................................................................................... 48
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 iv c ommand r egister cr4-( n ) ............................................................................................................ 48 figure 34.the digital local loop-back path within a given channel ............................................................. . 48 c ommand r egister cr4-( n ) ............................................................................................................ 48 4.3 t he r emote l oop -b ack m ode ................................................................................................... 49 figure 35.the remote loop-back path, within a given channel ................................................................... . 49 c ommand r egister cr4-( n ) ............................................................................................................ 49 4.4 t x off f eatures ......................................................................................................................... 50 c ommand r egister cr1-( n ) ............................................................................................................ 50 table 6:the relationship between the txoff input pin, the txoff bit field and the state of the transmitter 50 4.5 t he t ransmit d rive m onitor f eatures .................................................................................... 50 figure 36.the XRT73L04B employing the transmit drive monitor features ................................................. 51 4.6 t he taos (t ransmit a ll o ne s) f eature ................................................................................. 51 5.0 the microprocessor serial interface ................................................................................... 51 5.1 d escription of the c ommand r egisters .................................................................................. 51 c ommand r egister cr1-( n ) ............................................................................................................ 51 table 7:hexadecimal addresses and bit formats of XRT73L04B command registers ............................... 52 5.2 d escription of b it -f ields for each c ommand r egister ......................................................... 53 command register - cr0-(n) .................................................................................................... ........ 53 c ommand r egister cr 0-( n ) ............................................................................................................. 53 c ommand r egister cr1-( n ) ............................................................................................................ 54 command register cr2-(n) ...................................................................................................... ........ 54 c ommand r egister cr2-( n ) ............................................................................................................ 54 c ommand r egister cr3-( n ) ............................................................................................................ 55 c ommand r egister cr4-( n ) ............................................................................................................ 56 table 8:contents of llb_(n) and rlb_(n) and the corresponding loop-back mode for channel(n) ........... 56 5.3 o perating the m icroprocessor s erial i nterface . ................................................................. 56 figure 37.microprocessor serial interface data structure ...................................................................... ....... 57 figure 38.timing diagram for the microprocessor serial interface .............................................................. .. 58 o rdering information ..................................................................................................... 59 p ackage d imensions ........................................................................................................ 59 r evision h istory .............................................................................................................................. ....... 60
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 4 pin descriptions (by function) transmit interface p in #n ame t ype d escription 34 25 3 12 ttip_0 ttip_1 ttip_2 ttip_3 o transmit ttip output - channel (n): the XRT73L04B uses this pin along with tring_(n) to transmit a bipolar line signal via a 1:1 transformer. 32 23 5 14 tring_0 tring_1 tring_2 tring_3 o transmit ring output - channel (n): the XRT73L04B uses this pin along with ttip_(n) to transmit a bipolar line signal via a 1:1 transformer. 42 30 139 7 txclk_0 txclk_1 txclk_2 txclk_3 i transmit clock input for tpdata and tndata - channel (n): this input pin must be driven at 34.368 mhz (for e3 applications), 44.736 mhz (for ds3 applications), or 51.84 mhz (for sonet sts-1 applications). the XRT73L04B uses this signal to sample the tpdata_(n) and tndata_(n) input pins. by default, the XRT73L04B is configured to sample these two pins on the falling edge of this signal. n ote : if the XRT73L04B is operating in the host mode, then the device can be configured to sample the tpdata_(n) and tndata_(n) input pins on either the rising or falling edge of txclk_(n). 41 29 140 8 tpdata_0 tpdata_1 tpdata_2 tpdata_3 i transmit positive data input - channel (n) : the XRT73L04B samples this pin on the falling edge of txclk_(n). if the device samples a "1", then it generates and transmits a positive polarity pulse to the line. the data should be applied to this input pin if the transmit section is configured to accept single-rail data from the terminal equipment. n ote : if the XRT73L04B is operating in the host mode, then the XRT73L04B can be configured to sample the tpdata_(n) pin on either the rising or falling edge of txclk_(n). 40 28 141 9 tndata_0 tndata_1 tndata_2 tndata_3 i transmit negative data input - channel (n): the XRT73L04B samples this pin on the falling edge of txclk_(n). if the device samples a "1", then it generates and transmits a negative polarity pulse to the line. in single-rail mode, this pin must be tied to gnd to enable the hdb3/ b3zs encoder and decoder, (internally pulled-down). in dual-rail mode this input is the n-rail data input. n ote : if the XRT73L04B is operating in the host mode, then the XRT73L04B can be configured to sample the tndata_(n) pin on either the rising or falling edge of txclk_(n).
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 5 44 43 137 138 txlev_0 txlev_1 txlev_2 txlev_3 i transmit line build-out enable/disable select - channel (n): this input pin permits the transmit line build-out circuit, within channel (n), to be enabled or disabled. in e3 mode, this pin has no effect on the transmit pulse shape. setting this pin to "high" disables the line build-out circuit. in this mode, channel (n) outputs partially-shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. setting this pin to "low" enables the line build-out circuit within chan- nel (n). in this mode, channel (n) outputs shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. to comply with the isolated dsx-3/stsx-1 pulse template require- ments per bellcore gr-499-core or bellcore gr-253-core: 1. set this input pin to "1" if the cable length between the cross-connect and the transmit output of channel (n) is greater than 225 feet. 2. set this input pin to "0" if the cable length between the cross-connect and the transmit output of channel (n) is less than 225 feet. this pin is active only if the following two conditions are true: a. the XRT73L04B is configured to operate in either the ds3 or sonet sts-1 modes. b. the XRT73L04B is configured to operate in the hardware mode. n ote : this pin to should be tied to gnd if the XRT73L04B is going to be operating in the host mode, (internally pulled-down). 131 txoff i transmitter off input: setting this input pin "high" turns off all of the transmitter sections. in this mode the ttip and tring outputs are tri-stated. n otes : 1. this input pin controls the ttip and tring outputs even when the XRT73L04B is operating in the host mode. 2. for host mode operation, this pin is tied to gnd if the trans- mitter is intended to be turned off via the microprocessor serial interface. transmit interface p in #n ame t ype d escription
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 6 receive interface p in #n ame t ype d escription 59 53 121 127 rxclk_0 rxclk_1 rxclk_2 rxclk_3 or eceive clock output - channel (n): this output pin is the recovered clock signal from the incoming line sig- nal for channel (n). the receive section of channel (n) outputs data via the rpos_(n) and rneg_(n) output pins on the rising edge of this clock signal. configure the receive section of channel (n) to update the data on the rpos_(n) and rneg_(n) output pins on the falling edge of rxclk_(n) by doing one of the following: a. operating in the hardware mode pull the rxclkinv pin to "high". b. operating in the host mode write a "1" into the rxclkinv bit-field within the command register. 60 54 120 126 rneg_0/lcv_0 rneg_1/lcv_1 rneg_2/lcv_2 rneg_3/lcv_3 o receive negative data output - channel (n): the function of this pin is dependent on whether the 73l04a is in the hardware or host mode (host/hw ) and the condition of cs /(sr/dr ). a. operating in the hardware mode receive negative data: setting the cs /(sr/dr ) pin low, (dual-rail operation) this output pin pulses "high" whenever channel (n) has received a negative polarity pulse in the incoming line signal at the rtip_(n) and rring_(n) inputs. line code violation: when cs /(sr/dr ) is set high, (single-rail operation), the b3zs/hdb3 encoder/decoder is activated and the line code violation signal is out- put on this pin. b. operating in the host mode receive negative data: writing a 0 to the (sr/dr )_(n) bit in the command register configures channel(n) in the dual-rail mode and activates rneg_(n). writing a 1 to (sr/dr )_(n) bit of the command register configures the single-rail mode and activates lcv_(n). if the b3zs/hdb3 decoder is enabled then the zero suppression pat- terns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") is not reflected at this output. 61 55 119 125 rpos_0 rpos_1 rpos_2 rpos_3 o receive positive data output - channel (n): the function of this pin is dependent on the setting of the cs /(sr/dr ) pin. receive positive data if cs /(sr/dr ) is set low (dual-rail mode), this output pin pulses "high" whenever channel (n) has received a positive polarity pulse in the incoming line signal at the rtip_(n)/rring_(n) inputs. data output if cs /(sr/dr ) is set high (single-rail mode), data is output on this pin. if the b3zs/hdb3 decoder is enabled then the zero suppression pat- terns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") is not reflected at this output. 79 87 102 94 rring_0 rring_1 rring_2 rring_3 i receive ring input - channel (n): this input pin along with rtip_(n) is used to receive the bipolar line sig- nal from the remote ds3/e3/sts-1 terminal.
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 7 80 88 101 93 rtip_0 rtip_1 rtip_2 rtip_3 i receive tip input - channel (n): this input pin along with rring_(n) is used to receive the bipolar line sig- nal from the remote ds3/e3/sts-1 terminal. 82 90 99 91 reqen_0 reqen_1 reqen_2 reqen_3 i receive equalization enable input - channel (n): setting this input pin "high" enables the internal receive equalizer within channel (n). setting this pin "low" disables the internal receive equalizer. the guidelines for enabling and disabling the receive equal- izer are described in section 3.2. n ote : this pin is ignored and should be tied to gnd if the XRT73L04B is going to be operating in the host mode, (internally pulled-down). 110 rxclkinv i invert rxclk_(n) output - select: the function of this pin depends upon the mode of operation. hardware mode - invert rxclk output select: setting this input pin "high" configures the receive section of all chan- nels to invert their rxclk_(n) clock output signals. setting this pin "low" configures channel(n) to output the recovered data via the rpos_(n) and rneg_(n) output pins on the rising edge of rxclk_(n). setting this input pin "high" configures channel (n) to output the recov- ered data via the rpos_(n) and rneg_(n) output pins on the falling edge of rxclk_(n). n ote : this pin is internally pulled high. receive interface p in #n ame t ype d escription clock interface p in #n ame t ype d escription 66 57 115 123 exclk_0 exclk_1 exclk_2 exclk_3 i external reference clock input - channel (n): apply a 34.368 mhz clock signal for e3 applications, a 44.736 mhz clock signal for ds3 applications or a 51.84 mhz clock signal for sonet sts-1 applications. the channel (n) clock recovery pll uses this signal as a reference signal for declaring and clearing the receive loss of lock alarm. the clock recovery pll also generates the exact clock for the liu. it is permissible to use the same clock that drives the txclk_(n) input pin. it is permissible to operate the four channels at different data rates.
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 8 operating mode select p in #n ame t ype d escription 69 sr/dr /cs i microprocessor serial interface - chip select input/encoder- decoder disable input: the function of this pin depends upon whether the XRT73L04B is oper- ating in the host mode or in the hardware mode. n ote : this pin is internally pulled "high". hardware mode - receive output single-rail/dual-rail select: in hardware mode, setting this pin high configures each of the four channels to operate in the single-rail mode. when each of the four channels are configured to operate in the single-rail mode, then the receive section of each channel will output data via the rpos_(n) out- put pin. n ote : tie the tndata_(n) input to gnd to enable hdb3/b3zs encod- ing and decoding. setting this pin low configures each of the four channels to operate in the dual-rail mode. when each of the four channels are configured to operate in the dual-rail mode, then the receive section of each chan- nel will output data via both the rpos_(n) and rneg_(n) output pins. n ote : this input pin functions as the cs input pin, if the XRT73L04B device has been configured to operate in the host mode. 72 71 108 107 e3_0/sdo e3_1/sdi e3_2 e3_3 i/o i i i e3_mode select - channel 0: this pin has a dual function. in host mode, this pin functions as sdo. e3_mode select - channel 1 this pin has a dual function. in host mode,this pin functions as sdi. e3_mode select - channel 2 e3_mode select - channel 3 hardware mode operation - e3 mode select - channel (n): this input pin is used to configure channel (n) of the XRT73L04B to operate in the e3 or sts-1/ds3 modes. setting this input pin to "high" configures channel (n) to operate in the e3 mode. setting it "low" con- figures channel (n) to operate in either the ds3 or sts-1 modes, depending upon the state of the sts-1/ds3 _(n) input pin. n ote : this pin is internally pulled low when XRT73L04B is in the hardware mode. 73 83 106 98 sts1/ds3 _0 sts1/ds3 _1 sts1/ds3 _2 sts1/ds3 _3 i sts-1/ds3 select input - channel (n): high for sts-1 and low for ds3 operation. the XRT73L04B ignores this pin if the e3_(n) pin is set to "1". this input pin is ignored if the XRT73L04B is operating in the host mode. n ote : this pin should be tied to gnd if the XRT73L04B is going to be operating in the host mode, (internally pulled-down).
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 9 52 host/(hw )i host-hardware mode select: this input pin is used to enable or disable the microprocessor serial interface (e.g., consisting of the sdi, sdo, sclk, and cs pins). setting this input pin "high" enables the microprocessor serial interface (e.g. configures the XRT73L04B to operate in the host mode). in this mode, configure the XRT73L04B via the microprocessor serial interface. when the XRT73L04B is operating in the host mode, then it ignores the states of many of the discrete input pins. setting this input pin "low" disables the microprocessor serial interface (e.g., configures the XRT73L04B to operate in the hardware mode). in this mode, many of the external input control pins are functional. (internally pulled-up) operating mode select p in #n ame t ype d escription control and alarm interface p in #n ame t ype d escription 36 20 1 17 mring_0 mring_1 mring_2 mring_3 i monitor ring input - channel (n): the bipolar line output signal from tring_(n) can be connected to this pin via a 270-ohm resistor in order to check for line driver failure. this pin is internally pulled "high". 35 21 2 16 mtip_0 mtip_1 mtip_2 mtip_3 i monitor tip input - channel (n): the bipolar line output signal from ttip_(n) can be connected to this pin via a 270-ohm resistor in order to check for line driver failure. this pin is internally pulled "high". 48 26 133 11 dmo_0 dmo_1 dmo_2 dmo_3 o drive monitor output - channel (n): if no transmitted ami signal is present on mtip_(n) and mring_(n) input pins for 12832 txclk periods, then dmo_(n) toggles and remains "high" until the next ami signal is detected. 46 45 135 136 taos_0 taos_1 taos_2 taos_3 i transmit all ones select - channel (n): a "high" on this pin causes the transmit section, within channel (n), to generate and transmit a continuous ami all 1s" pattern onto the line. the frequency of this "1s" pattern is determined by txclk_(n). this input pin is ignored if the XRT73L04B is operating in the host mode. n ote : this pin should be tied to gnd if the XRT73L04B is going to be operating in the host mode, (internally pulled-down). 64 67 117 114 rlos_0 rlos_1 rlos_2 rlos_3 o receive loss of signal output indicator - channel (n): this output pin toggles "high" if channel (n) has detected a loss of sig- nal condition in the incoming line signal. the criteria that the XRT73L04B uses to declare an los condition depends upon whether the device is operating in the e3 or sts-1/ds3 mode. 65 68 116 113 rlol_0 rlol_1 rlol_2 rlol_3 o receive loss of lock output indicator - channel (n): this output pin toggles "high" if channel (n) has detected a loss of lock condition. channel (n) declares an lol (loss of lock) condition if the recovered clock frequency deviates from the reference clock frequency (available at the exclk_(n) input pin) by more than 0.5%.
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 10 60 54 120 126 rneg_0/(lcv_0) rneg_1/(lcv_1) rneg_2/(lcv_2) rneg_3/(lcv_3) o line code violation - channel (n): the function of this pin is dependent on whether the XRT73L04B is in the hardware or host mode (host/hw ) and if cs /(sr/dr ) is set high. hardware mode line code violation: when cs /(sr/dr ) is set high, (single-rail operation), the b3zs/hdb3 encoder/decoder is activated and the line code violation signal is out- put on this pin. host mode receive negative data: writing a 1 to (sr/dr )_(n) bit of the command register configures the single-rail mode and activates lcv_(n). if the b3zs/hdb3 decoder is enabled then the zero suppression pat- terns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") is not reflected at this output. 74 ict i in-circuit test input : setting this pin "low" causes all digital and analog outputs to go into a high-impedance state to allow for in-circuit testing. this pin should be set to "high" for normal operation. this pin is internally pulled "high". 75 losthr i loss of signal threshold control : forcing the losthr pin to gnd or vdd provides two settings. this pin must be set to a high or low level upon power up and should not be changed during operation. this pin is only applicable during ds3 or sts-1 operations. 76 84 105 97 llb_0 llb_1 llb_2 llb_3 i local loop-back - channel (n) : this input pin along with rlb_(n) dictates which loop-back mode chan- nel (n) is operating in. a "high" on this pin with rlb_(n) set to "low" configures channel (n) to operate in the analog local loop-back mode. a "high" on this pin with rlb_(n) also being set to "high" configures channel (n) to operate in the digital local loop-back mode. n ote : this pin is ignored and should be tied to gnd if the XRT73L04B is going to be operating in the host mode. 77 85 104 96 rlb_0 rlb_1 rlb_2 rlb_3 i remote loop-back - channel (n): this input pin in conjunction with llb_(n) dictates which loop-back mode channel (n) is operating in. a "high" on this pin with llb_(n) being set to "low" configures channel (n) to operate in the remote loop-back mode. a "high" on this pin with llb_(n) also being set to "high" configures channel (n) to operate in the digital local loop-back mode. n ote : this pin is ignored and should be tied to gnd if the XRT73L04B is going to be operating in the host mode. control and alarm interface p in #n ame t ype d escription
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 11 111 losmuten i mute-upon-los enable input (hardware mode): this input pin is use to configure the XRT73L04B, while it is operating in the hardware mode, to mute the recovered data via the rpos_(n), rneg_(n) output pins whenever one of the channels declares an los conditions. setting this input pin high" configures all channels to automatically pull the rpos_(n) and rneg_(n) output pins low whenever it is declaring an los condition, thereby muting the data being output to the terminal equipment. setting this input pin "low" configures all channels to not automatically mute the recovered data whenever an los condition is declared. n otes : 1. this pin is ignored and should be tied to gnd if the XRT73L04B is going to be operating in the host mode. 2. this pin is internally pulled "low". control and alarm interface p in #n ame t ype d escription microprocessor interface pin # name type description 69 cs/ sr/dr i microprocessor serial interface - chip select input/encoder- decoder disable input: the function of this pin depends upon whether the XRT73L04B is oper- ating in the host mode or in the hardware mode. host mode operation - chip select input: the local microprocessor must assert this pin to "0" in order to enable communication with the XRT73L04B via the microprocessor serial inter- face. n ote : this pin is internally pulled "high". 70 sclk/(rxoff) i microprocessor serial interface clock signal/receiver shut off input: the function of this pin depends upon: host mode - microprocessor serial interface clock signal: this signal is used to sample the data on the sdi pin on the rising edge of this signal. during read operations the microprocessor serial inter- face updates the sdo output on the falling edge of this signal. hardware mode - receiver shut off input: setting this input pin "high" shuts off all of the receiver sections. set- ting this input pin "low" enables all of the receive sections for full oper- ation. 71 sdi/e3_1 i serial data input for the microprocessor serial interface this pin has a dual function. host mode: to read or write data into the command registers over the microproces- sor serial interface, apply the read/write bit, the address values of the command registers and data value to be written during write opera- tions to this pin. this input is sampled on the rising edge of the sclk pin.
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 12 72 sdo/e3_0 o serial data output from the microprocessor serial interface the function of this pin depends upon the mode of operation. host mode operation: this pin serially outputs the contents of the specified command register during read operations. the data on this pin is updated on the falling edge of the sclk input signal. this pin is tri-stated upon completion of data transfer. 110 regr/ rxclkinv i register reset input (invert rxclk_(n) output - select): the function of this pin depends upon the mode of operation.in hard- ware mode, this pin functions as rxclkinv. host mode - register reset input: setting this input pin "low" causes the XRT73L04B to reset the contents of the command registers to their default settings and to its default operating configuration. n ote : this pin is internally pulled high. microprocessor interface pin # name type description
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 13 power and ground pins pin # name type description 4 txavdd_2 **** transmitter analog supply, 3.3v + 5% - channel(n) 6 txagnd_2 **** transmitter analog ground - channel(n) 10 txavdd_3 **** transmitter analog supply, 3.3v + 5% - channel(n) 13 txavdd_3 **** transmitter analog supply, 3.3v + 5% - channel(n) 15 txagnd_3 **** transmitter analog ground - channel(n) 18 txagnd_3 **** transmitter analog ground - channel(n) 19 txagnd_1 **** transmitter analog ground - channel(n) 22 txagnd_1 **** transmitter analog ground - channel(n) 24 txavdd_1 **** transmitter analog supply, 3.3v + 5% - channel(n) 27 txavdd_1 **** transmitter analog supply, 3.3v + 5% - channel(n) 31 txagnd_0 **** transmitter analog ground - channel(n) 33 txavdd_0 **** transmitter analog supply, 3.3v + 5% - channel(n) 47 txavdd_0 **** transmitter analog supply, 3.3v + 5% - channel(n) 49 txagnd_0 **** transmitter analog ground - channel (n) 50 agnd_0 **** analog ground pin - channel (n) 51 rxdvdd_1 **** receiver digital supply 3.3v + 5% channel (n) 56 rxdgnd_1 **** receiver digital ground - channel(n) 58 rxdvdd_0 **** receiver digital supply 3.3v + 5% channel (n) 62 rxdgnd_0 **** receiver digital ground - channel(n) 63 agnd_1 **** analog ground pin - channel(n) 78 rxavdd_0 **** receiver analog supply 3.3v + 5% - channel (n) 81 rxagnd_0 **** receiver analog ground - channel (n) 86 rxavdd_1 **** receiver analog supply 3.3v + 5% - channel (n) 89 rxagnd_1 **** receiver analog ground - channel (n) 92 rxagnd_3 **** receiver analog ground - channel (n) 95 rxavdd_3 **** receiver analog supply 3.3v + 5% - channel (n) 100 rxagnd_2 **** receiver analog ground - channel (n) 103 rxavdd_2 **** receiver analog supply 3.3v + 5% - channel (n) 109 agnd_2 **** analog ground pin - channel (n) 112 agnd_3 **** analog ground pin - channel (n) 118 rxdgnd_2 **** receiver digital ground - channel(n) 122 rxdvdd_2 **** receiver digital supply 3.3v + 5% - channel (n)
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 14 124 rxdgnd_3 **** receiver digital ground - channel(n) 128 rxdvdd_3 **** receiver digital supply 3.3v + 5% - channel (n) 129 exdgnda **** external clock digital ground 130 exdvdda **** external clock digital supply 132 txagnd_2 **** transmitter analog ground - channel (n) 134 txavdd_2 **** transmitter analog supply 3.3v + 5% - channel(n) power and ground pins pin # name type description no connection pins pin # name type description 37 nc no connection 38 nc no connection 39 nc no connection 142 nc no connection 143 nc no connection 144 nc no connection
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 15 electrical characteristics n ote : the XRT73L04B is assembled in a thermally enhanced package with an integral copper heat slug. the heat slug is solder plated and is exposed on the bottom of the package and is electrically connected to the internal ground connections of the device. this heat slug can be soldered to the mounting board if desired, but must be elec- trically isolated from any v dd connections. n ote : * not applicable to pins with pull-up or pull-down resistors. absolute maximum ratings storage temperature - 65c to + 150c operating temperature - 40c to + 85c supply voltage range -0.5v to +3.465v theta-ja 24 c/w theta-jc 5.5 c/w e lectrical c haracteristics (t a = 25 c, v dd = 3.3v + 5%, unless otherwise specified ) s ymbol p arameter m in . typ .m ax .u nits dc electrical characteristics dv dd digital dc supply voltage 3.135 3.3 3.465 v av dd analog dc supply voltage 3.135 3.3 3.465 v i cc supply current (measured while transmitting and receiving all "1s") 500 ma v il input low voltage * 0.8 v v ih input high voltage * 2.0 5.0 v v ol output low voltage, iout = -4.0ma * 0.4 v v oh output high voltage, iout = 4.0ma * 2.8 v i l input leakage current * 10 a
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 16 n otes : 1. all XRT73L04B digital inputs are designed to be ttl 5v compliant. 2. all XRT73L04B digital outputs are also ttl 5v compliant. however, these outputs will not drive to 5v nor will they accept external 5v pull-ups. e lectrical c haracteristics (c ontinued ) (t a = 25 c, v dd = 3.3v + 5%, unless otherwise specified ) ac e lectrical c haracteristics (s ee f igure 5) t erminal s ide t iming p arameters (s ee f igure 6 and f igure 7) -- {(n) = 0, 1, 2 or 3 } s ymbol p arameter m in . typ .m ax .u nits txclk_(n) clock duty cycle (sts-1/ds3) 30 50 70 % txclk_(n) clock duty cycle (e3) 30 50 70 % txclk_(n) frequency (sonet sts-1) 51.84 mhz txclk_(n) frequency (ds3) 44.736 mhz txclk_(n) frequency (e3) 34.368 mhz t rtx txclk_(n) clock rise time (10% to 90%) 3 5 ns t ftx txclk_(n) clock fall time (90% to 10%) 3 5 ns t tsu tpdata_(n)/tndata_(n) to txclk_(n) falling set up time 3 1.5 ns t tho tpdata_(n)/tndata_(n) to txclk_(n) falling hold time 3 1.5 ns t lcvo rxclk_(n) to rising edge of lcv_(n) output delay 2.5 ns t tdy ttip_(n)/tring_(n) to txclk_(n) rising propagation delay time 8 ns rxclk_(n) clock duty cycle 50 % rxclk_(n) frequency (sonet sts-1) 51.84 mhz rxclk_(n) frequency (ds3) 44.736 mhz rxclk_(n) frequency (e3) 34.368 mhz t co rxclk_(n) to rpos_(n)/rneg_(n) delay time 0 2.5 ns t rrx rxclk_(n) clock rise time (10% to 90%) 1.5 ns t frx rxclk_(n) clock fall time (10% to 90%) 1.5 ns c i input capacitance 10 pf c l load capacitance 10 pf
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 17 f igure 5. t ransmit p ulse a mplitude t est c ircuit for e3, ds3 and sts-1 r ates ( typical channel ) f igure 6. t iming d iagram of the t ransmit t erminal i nput i nterface r1 31.6 w r2 31.6 w channel (n) channel (n) txpos_(n) txneg_(n) txlineclk_(n) ttip_(n) tring_(n) tpdata_(n) tndata_(n) txclk_(n) only one channel shown 1:1 r3 75 w tpdata or tndata ttip or tring tclk t tsu t tho t rtx t ftx t tdy f igure 7. t iming d iagram of the r eceive t erminal o utput i nterface rclk t rrx t frx rpos or rneg lcv t lcvo t co
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 18 e lectrical c haracteristics (c ontinued ), (t a = 25 c, v dd = 3.3v + 5%, unless otherwise specified ) l ine s ide p arameters e3 a pplication t ransmit c haracteristics ( see f igure 5) s ymbol p arameter m in .t yp .m ax u nits transmit output pulse amplitude (measured at secondary output of transformer) 0.90 1.00 1.10 vpk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns transmit output pulse width ratio 0.95 1.00 1.05 transmit output jitter with jitter-free input @ txclk_(n) 0.02 0.05 uipp receive line characteristics receive sensitivity (length of cable) 1200 1400 feet interference margin -20 -15 db signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db occurrence of los to los declaration time 10 255 ui termination of los to los clearance time 10 255 ui intrinsic jitter (all 1s pattern) 0.02 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 30 ui jitter tolerance @ jitter frequency = 10khz 4 ui jitter tolerance @ jitter frequency = 800khz 0.15 0.20 ui
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 19 e lectrical c haracteristics (c ontinued ), (t a = 25 c, v dd = 3.3v + 5%, unless otherwise specified ) l ine s ide p arameters s onet sts-1 a pplication t ransmit c haracteristics (s ee f igure 5) s ymbol p arameter m in .t yp .m ax u nits transmit output pulse amplitude (measured with txlev=0) 0.65 0.75 0.90 vpk transmit output pulse amplitude (measured with txlev=1) 0.90 1.00 1.10 vpk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.90 1.00 1.10 transmit output jitter with jitter-free input @ txclk_(n) 0.02 0.05 ui receive line characteristics receive sensitivity (length of cable) 900 1100 feet signal level to declare or clear loss of signal (see table 5 ) mv intrinsic jitter (all 1s pattern) 0.02 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 400khz 0.15 0.35 ui
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 20 e lectrical c haracteristics (c ontinued ), (t a = 25 c, v dd = 3.3v + 5%, unless otherwise specified ) l ine s ide p arameters ds3 a pplication t ransmit c haracteristics ( see f igure 5) s ymbol p arameter m in .t yp .m ax u nits transmit output pulse amplitude (measured at 0 feet, txlev=0) 0.65 0.75 0.85 vpk transmit output pulse amplitude (measured at 0 feet, txlev=1) 0.90 1.00 1.10 vpk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.90 1.00 1.10 transmit output jitter with jitter-free input @ txclk_(n) 0.02 0.05 ui receive line characteristics receive sensitivity (length of cable) 900 1100 feet signal level to declare or clear loss of signal (see table 5 ) mv intrinsic jitter (all 1s pattern) 0.02 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 300khz (cat ii) 0.35 0.45 ui
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 21 figure 8, figure 9 and figure 10 present the pulse template requirements for the e3, ds3 and sts-1 rates. f igure 8. itu-t g.703 t ransmit o utput p ulse t emplate for e3 a pplications 0% 50% v = 100% 14.55ns nominal pulse 12.1ns (14.55 - 2.45) 17 ns (14.55 + 2.45) 8.65 ns 10% 10% 20% f igure 9. b ellcore gr-499-core t ransmit o utput p ulse t emplate for ds3 a pplications ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 - 0. 8 - 0 .7 - 0.6 - 0. 5 - 0.4 - 0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0 .7 0.8 0. 9 1 1.1 1.2 1.3 1.4 time, in ui normalized amplitude lower curve upper curve
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 22 n otes : 1. a5 is always "0". 2. r/w = "1" for "read" operations 3. r/w = "0" for "write" operations 4. a shaded pulse, denotes a dont care value. f igure 10. b ellcore gr-253-core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 - 0 . 9 -0. 8 -0.7 -0. 6 -0. 5 -0. 4 -0 . 3 -0. 2 -0. 1 0 0.1 0.2 0.3 0 .4 0.5 0.6 0.7 0 .8 0.9 1 1.1 1.2 1.3 1 .4 time, in ui normalized amplitude lower curve upper curve f igure 11. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 23 n ote : the load is 10pf e lectrical c haracteristics (c ontinued ), (t a = 25 c, v dd = 3.3v + 5%, unless otherwise specified ) m icroprocessor s erial i nterface t iming (s ee f igure 12) s ymbol p arameter m in .t yp .m ax u nits t 21 cs low to rising edge of sclk setup time 5 ns t 22 cs high to rising edge of sclk hold time 5 ns t 23 sdi to rising edge of sclk setup time 5 ns t 24 sdi to rising edge of sclk hold time 5 ns t 25 sclk "low" time 65 80 ns t 26 sclk "high" time 65 80 ns t 27 sclk period 160 ns t 28 cs low to rising edge of sclk hold time 5 ns t 29 cs "inactive" time 160 ns t 30 falling edge of sclk to sdo valid time 80 ns t 31 falling edge of sclk to sdo invalid time 65 ns t 32 rising edge of cs to high z 100 ns t 33 rise/fall time of sdo output 20 ns f igure 12. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 24 system description a functional block diagram of the XRT73L04B e3/ ds3/sts-1 transceiver ic is presented in figure 13. the XRT73L04B contains four separate channels with three distinct sections: ? the transmit section - channels 0, 1, 2, and 3 ? the receive section - channels 0, 1, 2, and 3 ? the microprocessor serial interface section the transmit section - channels 0, 1, 2, and 3 the transmit section, within each channel, accepts ttl/cmos level signals from the terminal equip- ment in either a single-rail or dual-rail format. the transmit section then takes this data and does the following: ? encode this data into the b3zs format if the ds3 or sonet sts-1 modes has been selected or into the hdb3 format if the e3 mode has been selected. ? convert the cmos level b3zs or hdb3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. ? drive these pulses onto the line via the ttip_(n) and tring_(n) output pins across a 1:1 trans- former. n ote : the transmit section drives a "1" (or a mark) onto the line by driving either a positive or negative polarity pulse across the 1:1 transformer within a given bit period. the transmit section drives a "0" (or a space) onto the line by driving no pulse onto the line. the receive section - channels 0, 1, 2 and 3 the receive section, within each channel, receives a bipolar signal from the line via the rtip and rring signals through a 1:1 transformer or 0.01f capaci- tor. the recovered clock and data outputs to the local terminal equipment in the form of cmos level sig- nals via the rpos_(n), rneg_(n) and rxclk_(n) output pins. the microprocessor serial interface the XRT73L04B can be configured to operate in ei- ther the hardware mode or the host mode. the XRT73L04B contains four identical channels. the microprocessor interface inputs are common to all channels. the descriptions that follow refer to channel(n) where (n) represents channel 0, 1, 2 or 3. a. operating in the hardware mode when the XRT73L04B is operating in the hardware mode, then the following is true: 1. the microprocessor serial interface block is dis- abled. 2. the XRT73L04B is configured via input pin set- tings. the XRT73L04B can be configured to operate in the hardware mode by tying the host/(hw ) input pin to gnd. each of the pins associated with the microprocessor serial interface takes on their alternative role as de- fined intable 1. when the XRT73L04B is operating in the hardware mode, all of the remaining input pins become active. b. operating in the host mode the XRT73L04B can be configured to operate in the host mode by tying the host/(hw ) input pin to vdd. when the XRT73L04B is operating in the host mode, then the following is true. 1. the microprocessor serial interface block is enabled. writing the appropriate data into the on- chip command registers makes many configura- tion selections. 2. all of the following input pins are disabled and should be connected to ground: ? pins 43, 44, 137 & 138 - txlev_(n) ? pins 45, 46, 135 & 136 taos_(n) ? pin 82, 90, 91 & 99 - reqen_(n) ? pin 77, 85, 96 & 104 - rlb_(n) ? pin 76, 84, 97 & 105 - llb_(n) ? pin 107 & 108 - e3_(n) ? pin 73, 83, 98 &106 - sts-1/ds3 _(n) t able 1: r ole of m icroprocessor s erial i nterface pins when the XRT73L04B is operating in the h ardware m ode p in #p in n ame f unction , while in hardware mode 69 cs /(sr/dr ) (sr/dr ) 70 sclk/(rxoff) rxoff 71 sdi/(e3_1) e3_1 72 sdo/(e3_0) e3_0 110 regr /(rxclkinv) rxclkinv
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 25 in host mode operation, the txoff input pins can be used to turn on or turn off the transmit output drivers within all channels concurrently. the intent behind this feature is to permit a system designed for redundancy to quickly switch out a defective line card and switch-in the back-up line card. 1.0 selecting the data rate each channel within the XRT73L04B can be config- ured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. fur- ther, each channel can be configured to operate in a mode/data rate that is independent of the other chan- nels. two methods are available to select the data rate for each channel of the XRT73L04B. 1.1 c onfiguring c hannel (n) for the following disscussion the reader should refer totable 2 to determine the appropriate address for each command register of each channel in the XRT73L04B. the command register description re- fers to cr(x)-(n), where (x) = 0 to 7 and (n) refers to a particular channel of the XRT73L04B. f igure 13. f unctional b lock d iagram of the XRT73L04B rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) txlev_(n) txoff channel 2 agc/ equalizer serial processor interface peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr sdi sdo sclk cs/(sr/dr) regr rtip_(n) rring_(n) reqen_(n) channel 0 channel 1 notes: 1. (n) = 0, 1, 2 , or 3 for respective channels 2. serial processor interface input pins are shared by the four channels in host mode and redefined in hardware mode. device monitor mtip_(n) mring_(n) dmo_(n) transmit logic duty cycle adjust ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder e3_(n) sts-1/ds3_(n) host/(hw) rlol_(n) exclk_(n) rxoff rxclkinv rxclk_(n) rpos_(n) rneg_(n)/ (lcv_(n)) channel 3 tx control
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 26 t able 2: h exadecimal a ddresses and b it f ormats of XRT73L04B c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 c hannel 0 0x00 cr0-0 ro rlol_0 rlos_0 alos_0 dlos_0 dmo_0 0x01 cr1-0 r/w txoff_0 taos_0 txclkinv_0 txlev_0 reserved 0x02 cr2-0 r/w reserved reserved alosdis_0 dlosdis_0 reqen_0 0x03 cr3-0 r/w (sr/dr )_0 losmut_0 rxoff rxclk_0inv reserved 0x04 cr4-0 r/w reserved sts-1/ds3 _0 e3_0 llb_0 rlb_0 0x05 cr5-0 r/w reserved reserved reserved reserved reserved 0x06 cr6-0 r/w reserved reserved reserved reserved reserved 0x07 cr7-0 r/w reserved reserved reserved reserved reserved c hannel 1 0x08 cr0-1 ro rlol_1 rlos_1 alos_1 dlos_1 dmo_1 0x09 cr1-1 r/w txoff_1 taos_1 txclkinv_1 txlev_1 reserved 0x0a cr2-1 r/w reserved reserved alosdis_1 dlosdis_1 reqen_1 0x0b cr3-1 r/w (sr/dr )_1 losmut_1 rxoff rxclk_1inv reserved 0x0c cr4-1 r/w reserved sts-1/ds3 _1 e3_1 llb_1 rlb_1 0x0d cr5-1 r/w reserved reserved reserved reserved reserved 0x0e cr6-1 r/w reserved reserved reserved reserved reserved 0x0f cr7-1 r/w reserved reserved reserved reserved reserved c hannel 2 0x10 cr0-2 ro rlol_2 rlos_2 alos_2 dlos_2 dmo_2 0x11 cr1-2 r/w txoff_2 taos_2 txclkinv_2 txlev_2 reserved 0x12 cr2-2 r/w reserved reserved alosdis_2 dlosdis_2 reqen_2 0x13 cr3-2 r/w (sr/dr )_2 losmut_2 rxoff rxclk_2inv reserved 0x14 cr4-2 r/w reserved sts-1/ds3 _2 e3_2 llb_2 rlb_2 0x15 cr5-2 r/w reserved reserved reserved reserved reserved 0x16 cr6-2 r/w reserved reserved reserved reserved reserved 0x17 cr7-2 r/w reserved reserved reserved reserved reserved
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 27 address: the register addresses are presented in the hexa- decimal format. type: the command registers are either read-only (ro) type of registers or read/write (r/w) type of regis- ters. the default value for each of the bit-fields within these reg- isters is "0". a. operating in the hardware mode. in order to configure individual channels into the ap- propriate mode, set the e3_(n), and the sts-1/ ds3 _(n) input pins (where n = 0, 1, 2, or 3) to the ap- propriate logic states, as presented below intable 3. b. operating in the host mode. to configure a channel into the appropriate mode, write the appropriate values into the sts-1/ds3 _(n) and e3_(n) bit-fields within the command register cr4-(n), as illustrated below (refer to table 2 for the correct address for each channel). table 4 relates the values of these two bit-fields to the selected data rates. c hannel 3 0x18 cr0-3 ro rlol_3 rlos_3 alos_3 dlos_3 dmo_3 0x19 cr1-3 r/w txoff_3 taos_3 txclkinv_3 txlev_3 reserved 0x1a cr2-3 r/w reserved reserved alosdis_3 dlosdis_3 reqen_3 0x1b cr3-3 r/w (sr/dr )_3 losmut_3 rxoff rxclk_3inv reserved 0x1c cr4-3 r/w reserved sts-1/ds3 _3 e3_3 llb_3 rlb_3 0x1d cr5-3 r/w reserved reserved reserved reserved reserved 0x1e cr6-3 r/w reserved reserved reserved reserved reserved 0x1f cr7-3 r/w reserved reserved reserved reserved reserved t able 2: h exadecimal a ddresses and b it f ormats of XRT73L04B c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 t able 3: s electing the d ata r ate for c hannel (n) via the e3_(n) and sts-1/ds3 _(n) input pins (h ardware m ode ) d ata r ate s tate of e3_ (n) p in s tate of sts-1/ds3 _ (n) p in m ode of b3zs/hdb3 e ncoder / d ecoder b locks e3 (34.368 mbps) 1 x (don't care) hdb3 ds3 (44.736 mbps) 00 b3zs sts-1 (51.84 mbps) 01 b3zs command register, cr4-(n) d4 d3 d2 d1 d0 x sts-1/(ds3 )_(n)) e3_(n) llb_(n) rlb_(n) x x xxx t able 4: s electing the d ata r ate for c hannel (n) via the sts-1/ds3 _(n) and the e3_(n) bit - fields within the a ppropriate c ommand r egister (host m ode ) s elected d ata r ate sts-1/ds3 _ (n) (d3) e3_ (n) (d2) e3 x (don't care) 1 ds3 0 0 sts-1 1 0
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 28 2.0 the transmit section figure 13 indicates that the transmit section within each channel of the XRT73L04B consists of the fol- lowing blocks: ? transmit logic block ? txclk_(n) duty cycle adjust block ? hdb3/(b3zs) encoder ? pulse shaping block the purpose of the transmit section is to take ttl/ cmos level data from the terminal equipment and encode it into a format such that it can: 1. be efficiently transmitted over coaxial cable at e3, ds3, or sts-1 data rates. 2. be reliably received by the remote terminal equipment at the other end of the e3, ds3, or sts-1 data link. 3. comply with the applicable pulse template requirements. 2.1 t he t ransmit l ogic b lock the purpose of the transmit logic block is to accept either dual-rail or single-rail (e.g., a binary data stream) ttl/cmos level data and timing information from the terminal equipment. 2.1.1 accepting dual-rail data from the termi- nal equipment whenever the XRT73L04B accepts dual-rail data from the terminal equipment, it does so via the fol- lowing input signals: ? tpdata_(n) ? tndata_(n) ? txclk_(n) figure 14 illustrates the typical interface for the trans- mission of data in a dual-rail format between the terminal equipment and the transmit section of the XRT73L04B. the manner that the liu handles dual-rail data is described below and illustrated in figure 15. the transmit section (of a channel) typically samples the data on the tpdata_(n) and tndata_(n) input pins on the falling edge of txclk_(n). f igure 14. t he typical interface for the t ransmission of d ata in a d ual -r ail f or - mat from the t ransmitting t erminal e quipment to the t ransmit s ection of a channel terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu transmit logic block txpos txneg txlineclk tpdata tndata txclk f igure 15. t he XRT73L04B s amples the data on the tpd ata and tnd ata input pins txclk tpdata tndata data 1 1 0
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 29 txclk_(n) is the clock signal that is of the selected data rate frequency, e3 = 34.368 mhz, ds3 = 44.736 mhz and sts-1 = 51.84 mhz. if the transmit sec- tion samples a "1" on the tpdata_(n) input pin, then the transmit section of the device generates a posi- tive polarity pulse via the ttip_(n) and tring_(n) output pins across a 1:1 transformer. if the transmit section samples a "1" on the tndata_(n) input pin, then the transmit section of the device generates a negative polarity pulse via the ttip_(n) and tring_(n) output pins across a 1:1 transformer. 2.1.2 accepting single-rail data from the ter- minal equipment to transmit data in a single-rail data from the termi- nal equipment, configure the XRT73L04B in the host mode. to configure channel(n) to accept single-rail da- ta from the terminal equipment: write a "1" into the (sr/dr) _(n) bit-field, within com- mand register cr3-(n) shown below. (please refer totable 2 for the address of the individual (n) chan- nel. the transmit section (of each channel) samples this input pin on the falling edge of the txclk_(n) clock signal and encodes this data into the appropriate bi- polar line signal across the ttip_(n) and tring_(n) output pins. n otes : 1. in this mode, the transmit logic block ignores the tndata_(n) input pin. 2. if the transmit section of a given channel is config- ured to accept single-rail data from the terminal equipment, the b3zs/hdb3 encoder must be enabled. figure 16 illustrates the behavior of the tpdata_(n) and txclk_(n) signals when the transmit logic block has been configured to accept single-rail data from the terminal equipment. 2.2 t he t ransmit c lock d uty c ycle a djust c ir - cuitry the on-chip pulse-shaping circuitry within the trans- mit section of each channel in the XRT73L04B gen- erates pulses of the appropriate shapes and width to meet the applicable pulse template requirements. the widths of these output pulses are defined by the width of the half-period pulses within the txclk_(n) signal. however, if the widths of the pulses within the txclk_(n) clock signal are allowed to vary significant- ly, this could jeopardize the chip's ability to generate transmit output pulses of the appropriate width and thereby not meet the pulse template requirement specification. consequently, the chip's ability to gen- erate compliant pulses could depend upon the duty cycle of the clock signal applied to the txclk_(n) input pin. the transmit clock duty cycle adjust circuitry ac- cepts clock pulses via the txclk_(n) input pin at duty cycles ranging from 30% to 70% and converts them to a 50% duty cycle. 2.3 t he hdb3/b3zs e ncoder b lock the purpose of the hdb3/b3zs encoder block is to aid in the clock recovery process at the remote ter- minal equipment by ensuring an upper limit on the number of consecutive zeros that can exist within the line signal. 2.3.1 b3zs encoding if the XRT73L04B has been configured to operate in the ds3 or sonet sts-1 modes, then the hdb3/ b3zs encoder blocks operate in the b3zs mode. when the encoder is operating in this mode, it pars- es through and searches the transmit binary data stream from the transmit logic block for the occur- command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved 1xxxx f igure 16. t he b ehavior of the tpd ata and t x c lk i nput s gnals , while the t ransmit l ogic b lock is a ccepting s ingle -r ail d ata from the t erminal e quipment txclk tpdata data 1 1 0
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 30 rence of three (3) consecutive zeros (e.g., "000"). if the b3zs encoder finds an occurrence of three con- secutive zeros, then it substitutes these three "0s", with either a "00v" or a "b0v" pattern. where: "b" represents a bipolar pulse that is compliant with the alternating polarity requirements of the ami (al- ternate mark inversion) line code; and "v" represents a bipolar violation (e.g., a bipolar pulse that violates the alternating polarity require- ments of the ami line code). the b3zs encoder decides whether to substitute with either the 00v" or the "b0v" pattern in order to insure that an odd number of bipolar pulses exist be- tween any two consecutive violation pulses. figure 17 illustrates the b3zs encoder at work with two separate strings of three (or more) consecutive zeros 2.3.2 hdb3 encoding if the XRT73L04B is configured to operate in the e3 mode, then the hdb3/b3zs encoder blocks operate in the hdb3 mode. when the encoder is operating in this mode, it parses through and searches the trans- mit data stream from the transmit logic block for the occurrence of four (4) consecutive zeros (e.g., "0000"). if the hdb3 encoder finds an occurrence of four consecutive zeros, then it substitutes these four "0s", with either a "000v" or a "b00v" pattern. the hdb3 encoder decides whether to substitute with ei- ther the "000v" or the "b00v" pattern in order to in- sure that an odd number of bipolar pulses exist be- tween any two consecutive violation pulses. figure 18 illustrates the hdb3 encoder at work with two separate strings of four (or more) consecutive ze- ros. 2.3.3 disabling the hdb3/b3zs encoder the XRT73L04B hdb3/b3zs encoder can be dis- abled by two methods. a. operating in the hardware mode. the hbd3/b3zs encoder blocks within all channels are disabled by setting the cs /(sr/dr) input pin to "1". n ote : by executing this step the hdb3/b3zs encoder and decoder blocks in all channels of the XRT73L04B are glo- bally disabled. f igure 17. a n e xample of b3zs e ncoding tclk tpos sr data encoded pdata encoded ndata 100 1 01 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001 1 0 1 0 1 1 1 0 001 1 00 01 0100 0 0 0 00 0 0 0 1 111 1 0 0 00 00000 0 1 0 0 0 0 01 01 01 01 01 01 01 01 1 10 10 1 0 10 1 0 1 line signal bv 0 v 0 0 0 f igure 18. a n e xample of hdb3 e ncoding tclk tpos sr data encoded pdata encoded ndata 100 1 01 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001 1 0 1 0 1 1 1 0 001 1 00 01 0100 0 0 0 00 0 0 0 1 11 11 0 00 0 00000 0 1 0 0 0 0 01 01 01 01 01 01 01 01 1 10 10 1 0 10 1 0 1 line signal bv 0 v 0 0 0 0
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 31 a. operating in the host mode. when the XRT73L04B is operating in the host mode, then the hdb3/b3zs encoders within each channel can be individually enabled or disabled. disable the hdb3/b3zs encoder block within chan- nel(n) by setting the (sr/dr )_(n) bit-field within com- mand register (cr3-(n)) to "1" as illustrated below. n ote : this method can only be used if the XRT73L04B is operating in the host mode. if either of these methods are used to disable the hdb3/b3zs encoder, then the liu transmits the data as received via the tpdata_(n) and tndata_(n) input pins. 2.4 t he t ransmit p ulse s haping c ircuitry the transmit pulse shaper circuitry consists of a transmit line build-out circuit which can be enabled or disabled by setting the txlev_(n) input pin or txlev_(n) bit-field to highor "low". the purpose of the transmit line build-out circuit is to permit config- uration of each channel to transmit an output pulse which is compliant to either of the following pulse template requirements when measured at the digital cross connect system. each of these bellcore spec- ifications state that the cable length between the transmit output and the digital cross connect sys- tem can range anywhere from 0 to 450 feet. the isolated dsx-3 pulse template requirement per bellcore gr-499-core is illustrated in figure 19 and the isolated stsx-1 pulse template requirement per bellcore gr-253-core is illustrated in figure 20. command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved 1xx x x f igure 19. t he b ellcore gr-499-core t ransmit o utput p ulse t emplate for ds3 a pplications ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 - 0.9 - 0.8 -0.7 -0.6 - 0. 5 - 0. 4 - 0.3 - 0.2 -0.1 0 0. 1 0. 2 0.3 0. 4 0. 5 0. 6 0. 7 0. 8 0.9 1 1. 1 1.2 1. 3 1. 4 time, in ui normalized amplitude lower curve upper curve
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 32 . 2.4.1 enabling the transmit line build-out cir- cuit if the transmit line build-out circuit is enabled, then the transmit section of the channel outputs shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. enable the transmit line build-out circuit for each channel by doing the following: a. operating in the hardware mode set the txlev_(n) input pin to low". b. operating in the host mode set the txlev_(n) bit-field to "0", as illustrated below. 2.4.2 disabling the transmit line build-out cir- cuit if the transmit line build-out circuit is disabled, then the XRT73L04B outputs partially shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. disable the transmit line build-out circuit by doing the following: a. operating in the hardware mode set the txlev_(n) input pin to high". b. operating in the host mode set the txlev_(n) bit-field to "1" as illustrated below. f igure 20. t he b ellcore gr-253-core t ransmit o utput p ulse t emplate for sonet sts-1 a ppli - cations sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0 .5 -0.4 -0 .3 -0.2 -0.1 0 0.1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0.8 0 .9 1 1 .1 1 .2 1.3 1 .4 time, in ui normalized amplitude lower curve upper curve command register, cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) reserved 0x x 0x
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 33 2.4.3 design guideline for setting the transmit line build-out circuit the txlev_(n) input pins or bit-fields should be set based upon the overall cable length between the transmitting terminal and the digital cross connect system where the pulse template measurements are made. if the cable length between the transmitting ter- minal and the dsx-3 or stsx-1 is less than 225 feet, enable the transmit line build-out circuit by setting the txlev_(n) input pin or bit-field to "0". n ote : in this case, the configured channel outputs shaped (e.g., not square-wave) pulses onto the line via its ttip_(n) and tring_(n) output pins. the shape of this output pulse is such that it complies with the pulse template require- ments even when subjected to cable loss ranging from 0 to 225 feet. if the cable length between the transmitting ter- minal and the dsx-3 or stsx-1 is greater than 225 feet, disable the transmit line build-out circuit by setting the txlev_(n) input pin or bit-field to "1". n ote : in this case, the configured channel outputs partially shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. the cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) cause these pulses to be properly shaped and comply with the appropriate pulse template requirement. 2.4.4 the transmit line build-out circuit and e3 applications the itu-t g.703 pulse template requirements for e3 states that the e3 transmit output pulse should be measured at the secondary side of the transmit out- put transformer for pulse template compliance. in other words, there is no digital cross connect sys- tem pulse template requirement for e3. consequent- ly, the transmit line build-out circuit within a given channel is disabled whenever that channel has been configured to operate in the e3 mode. 2.5 i nterfacing the t ransmit s ections of the XRT73L04B to the l ine the e3, ds3 and sonet sts-1 specification docu- ments all state that line signals transmitted over coax- ial cable are to be terminated with 75 ohm resistor. interface the transmit section of the XRT73L04B in the manner illustrated in figure 21. command register, cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) reserved 0x x 1x f igure 21. r ecommended s chematic for i nterfacing the t ransmit s ection of the XRT73L04B to the l ine r1 31.6 w r2 31.6 w channel (n) txpos_(n) txneg_(n) txlineclk_(n) ttip_(n) tring_(n) tpdata_(n) tndata_(n) txclk_(n) only one channel shown 1:1 j1 bnc
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 34 transformer vendor information pulse corporate office 12220 world trade drive san diego, ca 92128 tel: (858)-674-8100 fax: (858)-674-8262 europe 1 & 2 huxley road the surrey research park guildford, surrey gu2 5re united kingdom tel: 44-1483-401700 fax: 44-1483-401701 asia 150 kampong ampat #07-01/02 ka centre singapore 368324 tel: 65-287-8998 fax: 65-280-0080 website: http://www.pulseeng.com halo electronics corporate office p.o. box 5826 redwood city, ca 94063 tel: (650)568-5800 fax: (650)568-6165 email: info@haloelectronics.com website: http://www.haloelectronics.com transpower technologies, inc. corporate office park center west building 9805 double r blvd, suite # 100 reno, nv 89511 (800)500-5930 or (775)852-0140 email: info@trans-power.com website: http://www.trans-power.com transformer recommendations p arameter v alue turns ratio 1:1 primary inductance 40 m h isolation voltage 1500vrms leakage inductance 0.6 m h p art n umber v endor i nsulation p ackage t ype pe-68629 pulse 3000v large thru-hole pe-65966 pulse 1500v small thru-hole pe-65967 pulse 1500v small smt t3001 pulse 1500v small smt tg01-0406ns halo 1500v small smt tti 7601-sm trans-power 1500v small smt
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 35 3.0 the receive section figure 13 indicates the receive section consists of the following blocks: ? agc/equalizer ? peak detector ? slicer ? clock recovery pll ? data recovery ? hdb3/b3zs decoder the purpose of the receive section is to take an in- coming attenuated/distorted bipolar signal from the line and encode it back into the ttl/cmos format where it can be received and processed by the termi- nal equipment. 3.1 i nterfacing the r eceive s ections of the XRT73L04B to the l ine the design of the receive circuitry should be trans- former-coupled to the receive section to the line. the specification documents for e3, ds3, and sts-1 all specify 75 ohm termination loads when transmit- ting over coaxial cable. the recommended method to interface the receive section to the line in a manner is shown in figure 22. f igure 22. r ecommended s chematic for i nterfacing the r eceive s ection of the XRT73L04B to the l ine (t ransformer -c oupling ) j1 bnc t1 1:1 r1 37.4 w r2 37.4 w channel (n) rxpos_(n) rxneg_(n) rxclk_(n) rtip_(n) rring_(n) rpos_(n) rneg_(n) rxclk_(n) c1 0.01uf only one channel shown
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 36 3.2 t he r eceive e qualizer b lock the purpose of this block is to equalize the incoming distorted signal due to cable loss. the receive equalizer attempts to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably. . 3.2.1 guidelines for setting the receive equal- izer this data sheet presents guidelines for setting the receive equalizer, for the following conditions. 1. if the overall cable length, from the local receiv- ing terminal to the remote transmitting terminal is not known. 2. if the overall cable length, from the local receiv- ing terminal to the remote transmitting terminal is known. 3.2.1.1 if the overall cable length is not known this section presents recommendations on what state to set the receive equalizer when the overall cable-length, from the local receiving terminal to the remote transmitting terminal is not known. for ds3, sts-1 and e3 applications, enable the receive equalizer by setting either the reqen_(n) input pin high or the reqen_(n) bit-field to 1. the remain- der of this section provides an explanation why we recommend enabling the receive equalizer for these applications. 3.2.1.1.1 the use of the receive equalizer in a typical ds3 or sts-1 application most system manufacturers of equipment supporting ds3 and sts-1 lines, interface their equipment to ei- ther a dsx-3 or stsx-1 cross-connect. while in- stalling their equipment the transmit line build-out circuit is set to the proper setting that makes the transmit output pulse compliant with the isolated dsx-3 or stsx-1 pulse template requirements. for the XRT73L04B, this is achieved by setting the txlev_(n) input pin or bit-field to the appropriate lev- el. f igure 23. t he t ypical a pplication for the s ystem i nstaller digital cross-connect system transmitting terminal receiving terminal 0 to 450 feet of cable pulses that are compliant to the isolated dsx-3 or stsx-1 pulse template requirement 0 to 450 feet of cable dsx-3 or stsx-1
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 37 when the system manufacturer is interfacing the re- ceive section of the XRT73L04B to the cross-con- nect, they should be aware of the following facts: 1. all ds3 or sts-1 line signals that are present at either the dsx-3 or the stsx-1 cross connect are required to meet the isolated pulse template requirements per bellcore gr-499-core for ds3 applications, or bellcore gr-253-core for sts-1 applications. 2. bellcore documents state that the amplitude of these pulses at the dsx-3 or stsx-1 location can range in amplitude from 360mvpk to 850mvpk. bellcore documents stipulate that the receiving ter- minal must be able to receive the pulse template compliant line signal over a cable length of 0 to 450 feet from the dsx-3 or the stsx-1 cross-connect lo- cation. these facts are reflected in figure 23. design considerations for ds3 and sts-1 appli- cations when installing equipment into environments depict- ed in figure 23, the system installation personnel may be able to determine the cable length between the local terminal equipment and the dsx-3/stsx-1 cross-connect patch-panel. the cable length be- tween the local terminal equipment and the dsx-3/ stsx-1 cross-connect patch panel ranges between 0 and 450 feet. it is extremely unlikely that the system installation personnel will know the cable length between the dsx-3/stsx-1 cross-connect patch-panel and the remote terminal equipment. therefore, we recom- mend that the receive equalizer be enabled by set- ting the reqen_(n) input pin or bit-field to 1. the only time that the receive equalizer should be disabled is when there is an off-chip equilizer in the receive path between the dsx-3/stsx-1 cross- connect and the rtip_(n)/rring_(n) input pins, or in applications where the receiver is directly monitor- ing the transmit output signal directly. 3.2.1.2 design considerations for e3 applica- tions in e3 system installation, it is recommended that the receive equalizer of the XRT73L04B be enabled by pulling the reqen_(n) input pins high or by setting the reqen_(n) bit-fields to 1. n ote : the results of extensive testing indicates that when the receive equalizer is enabled, the XRT73L04B is capa- ble of receiving an e3 line signal with anywhere from 0 to 12db of cable loss over the industrial temperature range. ? design considerations for e3 applications or if the overall cable length is known if during system installation the overall cable length is known, then in order to optimize the performance of the XRT73L04B in terms of receive intrinsic jitter, etc., enable or disable the receive equalizer based upon the following recommendations: the receive equalizer should be turned on if the receive section of a given channel is going to re- ceive a line signal with an overall cable length of 300 feet or greater. conversely, turn off the receive equalizer if the receive section of a given channel is going to receive a line signal over a cable length of less than 300 feet. n otes : 1. if the receive equalizer block is turned on when it is receiving a line signal over short cable length, the received line signal may be over-equalized which could degrade performance by increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors 2. the receive equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the trans- mitting terminal to the receiving terminal. however, the receive equalizer was not designed to counter flat loss where all of the fourier frequency compo- nents within the line signal are subject to the same amount of attenuation. flat loss is handled by the agc block. disable the receive equalizer block by doing either of the following. a. operating in the hardware mode setting the reqen_(n) input pin low". b. operating in the host mode writing a "0" to the reqen_(n) bit-field within com- mand register cr2, as illustrated below. command register cr-2(n) d4 d3 d2 d1 d0 reserved reserved alosdis_(n) dlosdis_(n) reqen_(n) xxxx 0
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 38 3.3 c lock r ecovery pll the purpose of the clock recovery pll is to track the incoming dual-rail data stream and to derive and generate a recovered clock signal. it is important to note that the clock recovery pll re- quires a line rate clock signal at the exclk_(n) input pin. the clock recovery pll operates in one of two modes: ? the training mode. ? the data/clock recovery mode 3.3.1 the training mode if a given channel is not receiving a line signal via the rtip and rring input pins, or if the frequency differ- ence between the line signal and that applied via the exclk_(n) input pin exceeds 0.5%, then the channel operates in the training mode. when the channel is operating in the training mode, it does the following: a. declare a loss of lock indication by toggling its respective rlol_(n) output pin high". b. output a clock signal via the rxclk_(n) output pins which is derived from the signal applied to the exclk_(n) input pin. 3.3.2 the data/clock recovery mode if the frequency difference between the line signal and that applied via the exclk_(n) input pin is less than 0.5%, then the channel operates in the data/ clock recovery mode. in this mode, the clock re- covery pll locks onto the line signal via the rtip and rring input pins. 3.4 t he hdb3/b3zs d ecoder the remote transmitting terminal typically encodes the line signal into some sort of zero suppression line code (e.g., hdb3 for e3, and b3zs for ds3 and sts-1). the purpose of this encoding activity was to aid in the clock recovery process of this data within the near-end receiving terminal. however, once the data has made it across the e3, ds3 or sts-1 trans- port medium and has been recovered by the clock recovery pll, it is now necessary to restore the orig- inal content of the data. hence, the purpose of the hdb3/b3zs decoding block is to restore the data transmitted over the e3, ds3 or sts-1 line to its orig- inal content prior to zero suppression coding. 3.4.1 b3zs decoding (ds3/sts-1 applications) if the XRT73L04B is configured to operate in the ds3 or sts-1 modes, then the hdb3/b3zs decoding blocks performs b3zs decoding. when the decod- ers are operating in this mode, each of the decoders parses through its respective incoming dual-rail data and checks for the occurrence of either a 00v" or a "b0v" pattern. if the b3zs decoder detects this par- ticular pattern, then it substitutes these bits with a "000" pattern. n ote : if the b3zs decoder detects any bipolar violations that is not in accordance with the b3zs line code format, or if the b3zs decoder detects a string of 3 (or more) con- secutive "0s in the incoming line signal, then the b3zs decoder flags this event as a line code violation by puls- ing the lcv output pin high". figure 24 illustrates the b3zs decoder at work with two separate zero suppression patterns in the in- coming dual-rail data stream. 3.4.2 hdb3 decoding (e3 applications) if the XRT73L04B is configured to operate in the e3 mode, then each of the hdb3/b3zs decoding blocks performs hdb3 decoding. when the decoders are operating in this mode, they each parse through the incoming dual-rail data and check for the occurrence of either a "000v" or a "b00v" pattern. if the hdb3 f igure 24. a n e xample of b3zs d ecoding data 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 rpos rneg 0 0 v line signal b 0 v rclk
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 39 decoder detects this particular pattern, then it substi- tutes these bits with a 0000" pattern. figure 25 illustrates the hdb3 decoder at work with two separate zero suppression patterns, in the in- coming dual-rail data stream. n ote : if the hdb3 decoder detects any bipolar violation (e.g., "v") pulses that is not in accordance with the hdb3 line code format, or if the hdb3 decoder detects a string of 4 (or more) "0's" in the incoming line signal, then the hdb3 decoder flags this event as a line code violation by pulsing the lcv output pin high". 3.4.3 configuring the hdb3/b3zs decoder the XRT73L04B can enable or disable the hdb3/ b3zs decoder blocks by either of the following means. a. operating in the host mode enable the hdb3/b3zs decoder block of channel(n) by writing a "0" into the (sr/dr )_(n) bit-field within command register cr3-(n), as illustrated below. b. operating in the hardware mode to globally enable all hdb3/b3zs decoder blocks, pull the cs /(sr/dr )_(n) input pin "low". to globally disable all hdb3/b3zs decoder blocks and configure the device to transmit and receive in an ami format by pulling the cs / (sr/dr )_(n) input pin "high". 3.5 los d eclaration /c learance each channel contains circuitry that monitors the fol- lowing two parameters associated with the incoming line signals. 1. the amplitude of the incoming line signal via the rtip and rring inputs. 2. the number of pulses detected in the incoming line signal within a certain amount of time. if a given channel determines that the incoming line signal is missing either due to insufficient amplitude or a lack of pulses in the incoming line signal, then it declares a loss of signal (los) condition. the chan- nel declares the los condition by toggling its respec- tive rlos_(n) output pin high" and by setting its cor- responding rlos_(n) bit field within command reg- ister 0 (or command register 8) to "1". conversely, if the channel determines that the incom- ing line signal has been restored (e.g., there is suffi- cient amplitude and pulses in the incoming line sig- nal), then it clears the los condition by toggling its respective rlos_(n) output pin low" and setting its corresponding rlos_(n) bit-field to "0". in general, the los declaration/clearance scheme that is employed in the XRT73L04B is based upon itu-t recommendation g.775 for both e3 and ds3 applications. 3.5.1 the los declaration/clearance criteria for e3 applications f igure 25. a n e xample of hdb3 d ecoding data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 v line signal b 0 0 v rpos rneg rclk command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved 0xx x x
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 40 when the XRT73L04B is operating in the e3 mode, a given channel declares an los condition if its re- ceive line signal amplitude drops to -35db or below. further, the channel clears the los condition if its receive line signal amplitude rises back to -15db or above. figure 26 illustrates the signal levels at which each channel of the XRT73L04B declares and clears los. timing requirements associated with declaring and clearing the los indicator the XRT73L04B was designed to meet the itu-t g.775 specification timing requirements for declaring and clearing the los indicator. in particular, a chan- nel declares an los between 10 and 255 ui (or e3 bit-periods) after the actual time the los condition occurred. further, the channel clears the los indica- tor within 10 to 255 ui after restoration of the incom- ing line signal. figure 27 illustrates the los declara- tion and clearance behavior in response to the loss of signal event and then the restoration of the signal. f igure 26. t he s ignal l evels that the XRT73L04B declares and clears los 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 41 3.5.2 the los declaration/clearance criteria for ds3 and sts-1 applications when the XRT73L04B is operating in the ds3 or sts-1 mode, then each channel declares and clears los based upon the following two criteria. ? analog los (alos) declaration/clearance crite- ria ? digital los (dlos) declaration/clearance crite- ria in the ds3 mode, the los output (rlos) is simply the logical "or" of the alos and dlos states. 1. the analog los (alos) declaration/clearance criteria a channel declares an analog los (alos_(n)) con- dition if the amplitude of the incoming line signal drops below a specific amplitude as defined by the voltage at the losthr input pin, and whether the receive equalizer is enabled or not. table 5 presents the various voltage levels at the losthr input pin, the state of the receive equalizer and the corresponding alos (analog los) threshold amplitudes. declaring alos a channel(n) declares alos_(n) whenever the ampli- tude of the receive line signal falls below the signal level to declare alos levels, as specified intable 5. clearing alos_(n) a channel(n) clears alos_(n) whenever the ampli- tude of the receive line signal increases above the signal level to clear alos levels, as specified in table 5. there is approximately a 2db hysteresis in the re- ceived signal level that exists between declaring and f igure 27. t he b ehavior of the los o utput i ndicator in response to the l oss of s ignal and the r es - toration of s ignal actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 compliance g.775 compliance 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rtip/ rring rlos output pin t able 5: t he alos (a nalog los) d eclare and c lear t hresholds for a given setting of losthr and reqen (ds3 and sts-1 a pplications ) a pplication reqen s etting losthr s etting s ignal l evel to d eclare alos s gnal l evel to c lear alos ds3 1 1 < 22mv > 90mv 01< 17mv < 70mv sts-1 1 1 < 25mv > 115mv 01< 20mv < 90mv
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 42 clearing alos_(n) in order to prevent chattering in the rlos_(n) output signal. monitoring the state of alos_(n) if the XRT73L04B is operating in the host mode, the state of alos_(n) of channel(n) can be polled or monitored by reading in the contents of command register cr0. . if the alos_(n) bit-field contains a "1", then the cor- responding channel(n) is currently declaring an alos condition. conversely, if the alos_(n) bit-field contains a "0", then the channel is not currently de- claring an alos condition. disabling the alos detector for debugging purposes, it may be useful to disable the alos detector. if the XRT73L04B is operating in the host mode, disable the channel(n) alos de- tector by writing a "1" into the alosdis_(n) bit-field in command register cr2. 2. the digital los (dlos) declaration/clearance criteria a given channel(n) declares a digital los (dlos_(n)) condition if the XRT73L04B detects 16032 or more consecutive "0s" in the incoming da- ta. the channel clears dlos if it detects four consecu- tive sets of 32 bit-periods, each of which contains at least 10 "1s" (e.g., average pulse density of greater than 33%). monitoring the state of dlos if the XRT73L04B is operating in the host mode the state of dlos_(n) of channel(n) can be polled or monitored by reading in the contents of command register cr0. if the dlos_(n) bit-field contains a 1, then the cor- responding channel(n) is currently declaring a dlos condition. if the dlos_(n) bit-field contains a 0, then the channel(n) is currently declaring the dlos condition. disabling the dlos detector for debugging purposes, it is useful to disable the dlos_(n) detector. if the XRT73L04B is operating in the host mode, the dlos detector can be disabled by writing a 1 into the dlosdis_(n) bit-field in com- mand register cr2. n ote : setting both the alosdis_(n) and dlosdis_(n) bit-fields to "1" disables los declaration by channel(n). 3.5.3 muting the recovered data while the los is being declared command register cr0-(n) d4 d3 d2 d1 d0 rlol_(n) rlos_(n) alos_(n) dlos_(n) dmo_(n) read only read only read only read only read only command register cr2-(n) d4 d3 d2 d1 d0 reserved reserved alosdis_(n) dlosdis_(n) reqen_(n) xx 1xx command register cr0-(n) d4 d3 d2 d1 d0 rlol_(n) rlos_(n) alos_(n) dlos_(n) dmo_(n) read only read only read only read only read only command register cr2-(n) d4 d3 d2 d1 d0 reserved reserved alosdis_(n) dlosdis_(n) reqen_(n) xxx 1x
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 43 in some applications it is not desirable for a channel within the e3/ds3/sts-1 liu to recover data and route it to the receiving terminal while the channel is declaring an los condition. consequently, the XRT73L04B includes an los muting feature. this feature, if enabled, causes a given channel to halt transmission of the recovered data to the receiving terminal while the los condition is "true". in this case, the rpos_(n) and rneg_(n) output pins are forced to "0". once the los condition has been cleared, then the channel(n) resumes normal trans- mission of the recovered data to the receiving termi- nal. this feature is available whenever XRT73L04B is op- erating in the host mode or hardware mode. a. operating in the hardware mode. the muting upon los feature is enabled by pulling the losmuten output pin high". this enables the muting upon los feature globally for all channels. b. operating in the host mode. the muting upon los feature for each channel can be enabled by writing a "1" into the losmut_(n) bit- field within command register 3. n ote : this step only enables the muting upon los feature within channel(n). 3.6 r outing the r ecovered t iming and d ata i nformation to the r eceiving t erminal e quipment each channel ultimately takes the recovered timing and data information, converts it into cmos levels and routes it to the receiving terminal equipment via the rpos_(n), rneg_(n) and rxclk_(n) output pins. each channel can deliver the recovered data and clock information to the receiving terminal in either a single-rail or dual-rail format. 3.6.1 routing dual-rail format data to the receiving terminal equipment whenever a channel delivers dual-rail format to the terminal equipment, it does so via the following sig- nals. ? rpos_(n) ? rneg_(n) ? rxclk_(n) figure 28 illustrates the typical interface for the trans- mission of data in a dual-rail format from the re- ceive section of a channel to the receiving terminal equipment. . the manner that a given channel transmits dual-rail data to the receiving terminal equipment is de- scribed below and illustrated in figure 29. each channel(n) typically updates the data on the command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved x 1x x x x f igure 28. t he typical interface for the t ransmission of d ata in a d ual -r ail f ormat , from the r eceive s ection of the XRT73L04B to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block rxpos rxneg rxclk rpos rneg rxclk
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 44 rpos_(n) and rneg_(n) output pins on the rising edge of rxclk_(n). rxclk_(n) is the recovered clock signal from the in- coming received line signal. as a result, these clock signals are typically 34.368 mhz for e3 applications, 44.736 mhz for ds3 applications and 51.84 mhz for sonet sts-1 applications. in general, if a given channel received a positive-po- larity pulse in the incoming line signal via the rtip_(n) and rring_(n) input pins, then the channel pulses its corresponding rpos_(n) output pin high". conversely, if the channel received a negative-polari- ty pulse in the incoming line signal via the rtip_(n) and rring_(n) input pins, then the channel(n) pulses its corresponding rneg_(n) output pin high". inverting the rxclk_(n) outputs each channel can invert the rxclk_(n) signals with respect to the delivery of the rpos_(n) and rneg_(n) output data to the receiving terminal equipment. this feature may be useful for those cus- tomers whose receiving terminal equipment logic design is such that the rpos_(n) and rneg_(n) da- ta must be sampled on the rising edge of rxclk_(n). figure 30 illustrates the behavior of the rpos_(n), rneg_(n) and rxclk_(n) signals when the rxclk_(n) signal has been inverted. in the hardware mode: setting the rxclkinv pin high results in all chan- nels of the XRT73L04B to output the recovered data on rpos_(n) and rneg_(n) on the falling edge of rxclk_(n). setting this pin low results in the recov- ered data on rpos_(n) and rneg_(n) to output on the rising edge of rxclk_(n). a. operating in the host mode in order to configure a channel(n) to invert the rxclk_(n) output signal, the XRT73L04B must be op- erating in the host mode. to invert rxclk_(n), associated with channel(n), write a "1" into the rxclk_(n)inv bit-field within com- mand register cr-3. f igure 29. h ow the XRT73L04B outputs data on the rpos and rneg output pins rxclk rpos rneg f igure 30. t he b ehavior of the rpos, rneg, and r x c lk signals when r x c lk is inverted rxclk rpos rneg
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 45 b. operating in the hardware mode setting the rxclkinv input pin high" inverts all the rxclk_(n) output signals. 3.6.2 routing single-rail format (binary data stream) data to the receive terminal equipment to route single-rail format data (e.g., a binary data stream) from the receive section of a channel to the receiving terminal equipment, do the following. a. operating in the host mode to configure channel(n) to output single-rail data to the terminal equipment, write a "1" into the (sr/ dr )_(n) bit-field within command register cr3-(n). the configured channel outputs single-rail data to the receiving terminal equipment via its correspond- ing rpos_(n) and rxclk_(n) output pins, as illustrat- ed in figure 31 and figure 32. b. operating in the hardware mode the XRT73L04B is configure to output dual-rail data from the receive sections of all channels by pulling the (sr/dr ) pin to gnd. the XRT73L04B is configure to output single-rail data from the receive sections of all channels by pulling the (sr/dr ) pin to vdd. n ote : when the XRT73L04B is operating in the hardware mode, the setting of the (sr/dr ) input pin applies globally to all channels. . command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved xxx 1 x command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved 1xx x x f igure 31. t he typical interface for the t ransmission of d ata in a s ingle -r ail f ormat from the r eceive s ection of the XRT73L04B to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block rxpos rxclk rpos rxclk
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 46 n ote : the rneg_(n) output pin is internally tied to ground whenever this feature is implemented. 3.7 s hutting off the r eceive s ection the receive section of each channel in the XRT73L04B can be shut off. this feature may come in handy in some redundant system designs. particu- larly, in those designs where the receive termination within the secondary liu line card has been switched-out and is not receiving any traffic in parallel with the primary line card. in this case, having the liu on the secondary line card consume the normal amount of current is a waste of power. this feature can permit powering down the receive section of the lius on the secondary line card which reduces their power consumption by approximately 80% a. operating in the hardware mode shut off the receive sections by pulling the rxoff input pin high". turn on the receiver sections by pulling the rxoff input pin to low". b. operating in the host mode shut off the receive sections by writing a "1" into the rxoff bit-field within command register cr3-(n). turn on the receive section of channel(n) by writing a "0" into the rxoff bit-field within command regis- ter cr3-(n). f igure 32. t he behavior of the rpos and r x c lk output signals while the XRT73L04B is transmit - ting s ingle -r ail data to the r eceiving t erminal e quipment rxclk rpos command register cr3-(n) d4 d3 d2 d1 d0 (sr/dr )_(n) losmut_(n) rxoff rxclk_(n)inv reserved xx 1x x
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 47 4.0 diagnostic features of the XRT73L04B the XRT73L04B supports equipment diagnostic ac- tivities by supporting the following loop-back modes within each channel. ? analog local loop-back. ? digital local loop-back ? remote loop-back n ote : in this data sheet we use the convention that chan- nel(n) refers to either channel 0, 1, 2 or 3. similarly, specific input and output pins uses this convention to denote which channel it is associated with. 4.1 t he a nalog l ocal l oop -b ack m ode when a given channel is configured to operate in the analog local loop-back mode, the channel ignores any signals that are input to its rtip_(n) and rring_(n) input pins. the transmitting terminal equipment transmits clock and data into this channel via the tpdata_(n), tndata_(n) and txclk_(n) input pins. this data is processed through the transmit clock duty cycle adjust pll and the hdb3/b3zs encoder. finally, this data is output to the line via the ttip_(n) and tring_(n) output pins. additionally, this data which is being output via the ttip_(n) and tring_(n) output pins is also looped back into the at- tenuator/receive equalizer block. consequently, this data is processed through the entire receive section of the channel. after this post-loop-back data has been processed through the receive section it out- puts to the near-end receiving terminal equipment via the rpos_(n), rneg_(n) and rxclk_(n) output pins. figure 33 illustrates the path that the data takes when the channel is configured to operate in the analog lo- cal loop-back mode. configure a given channel to operate in the analog local loop-back mode by employing either one of the following two steps a. operating in the host mode n ote : see table 2 for a description of command regis- ters and addresses for the different channels. to configure channel (n) to operate in the analog lo- cal loop-back mode, write a 1" into the llb_(n) bit- field and a "0" into the rlb_(n) bit-field within com- mand register cr4. f igure 33. a channel operating in the a nalog l ocal l oop -b ack m ode agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs/(sr/dr) regr rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) notes: 1. (n) = 0, 1, 2, or 3 for respective channels 2. serial processor interface input pins are shared by the four channels in host mode and redefined in hardware mode. rlol_(n) exclk_(n) device monitor mtip_(n) mring_(n) transmit logic duty cycle adjust txlev_(n) txoff_(n) dmo_(n) ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder serial processor interface analog local loop-back path
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 48 b. operating in the hardware mode to configure channel (n) to operate in the analog lo- cal loop-back mode, set the llb_(n) input pin (pin 76, 84, 97 or 105) high" and the rlb_(n) input pin (pin 77, 85, 96 or 104) "low". 4.2 t he d igital l ocal l oop -b ack m ode . when a given channel is configured to operate in the digital local loop-back mode, the channel ignores any signals that are input to the rtip and rring in- put pins. the transmitting terminal equipment trans- mits clock and data into the XRT73L04B via the tp- data, tndata and txclk input pins. this data is pro- cessed through the transmit clock duty cycle adjust pll and the hdb3/b3zs encoder block. at this point, this data is looped back to the hdb3/b3zs de- coder block. after this post-loop-back data has been processed through the hdb3/b3zs decoder block, it outputs to the near-end receiving terminal equip- ment via the rpos, rneg and rxclk output pins. figure 34 illustrates the path that the data takes when the chip is configured to operate in the digital local loop-back mode. configure a channel to operate in the digital local loop-back mode by employing either one of the fol- lowing two-steps: a. operating in the host mode to configure channel (n) to operate in the digital lo- cal loop-back mode, write a "1" into both the llb and rlb bit-fields within command register cr4-(n). command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/ds3 _(n) e3_(n) llb_(n) rlb_(n) xx x 1 0 f igure 34. t he d igital l ocal l oop -b ack path within a given channel agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs/(sr/dr) regr rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) notes: 1. (n) = 0, 1, 2, or 3 for respective channels 2. serial processor interface input pins are shared by the four channels in host mode and redefined in hardware mode. rlol_(n) exclk_(n) device monitor mtip_(n) mring_(n) transmit logic duty cycle adjust txlev_(n) txoff_(n) dmo_(n) ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder serial processor interface digital local loop-back path command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/ds3 _(n) e3_(n) llb_(n) rlb_(n) xx x 1 1
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 49 b. operating in the hardware mode. to configure channel (n) to operate in the digital lo- cal loop-back mode, pull both the llb input pin and the rlb input pin "high". 4.3 t he r emote l oop -b ack m ode when a given channel is configured to operate in the remote loop-back mode, the channel ignores any signals that are input to the tpdata and tndata input pins. the channel receives the incoming line signal via the rtip and rring input pins. this data is pro- cessed through the entire receive section and is out- put to the receive terminal equipment via the rpos, rneg and rxclk output pins. additionally, this data is also internally looped back into the pulse-shaping block within the transmit section. at this point, this data is routed through the remainder of the transmit section of the channel and transmitted out onto the line via the ttip_(n) and tring_(n) output pins. figure 35 illustrates the path that the data takes when the chip is configured to operate in the remote loop- back mode. configure a channel to operate in the remote loop- back mode by employing either one of the following two steps a. operating in the host mode to configure channel (n) to operate in the remote loop-back mode, write a "1" into the rlb bit-field, and a "0" into the llb bit-field, within command reg- ister cr4. b. operating in the hardware mode to configure channel(n) to operate in the remote loop-back mode, pull both the rlb_(n) input pin to high" and the llb_(n) input pin to "low". f igure 35. t he r emote l oop -b ack path , within a given channel agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs/(sr/dr) regr rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) notes: 1. (n) = 0, 1, 2, or 3 for respective channels 2. serial processor interface input pins are shared by the four channels in host mode and redefined in hardware mode. rlol_(n) exclk_(n) device monitor mtip_(n) mring_(n) transmit logic duty cycle adjust txlev_(n) txoff_(n) dmo_(n) ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder serial processor interface remote loop-back path command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/ds3 _(n) e3_(n) llb_(n) rlb_(n) xx x 0 1
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 50 4.4 t x off f eatures the transmit section of each channel in the XRT73L04B can be shut off. when this feature is in- voked, the transmit section of the configured chan- nel is shut-off and the transmit output signals (e.g., ttip_(n) and tring_(n)) is tri-stated. this feature is useful for system redundancy conditions or during di- agnostic testing. a. operating in the hardware mode shut off the transmit driver concurrently within all channels by toggling the txoff input pin high". turn on the transmit driver by toggling the txoff in- put pin low". b. operating in the host mode turn off the transmit driver within channel(n) by set- ting the txoff_(n) bit-field within command register cr1-(n) to "1". writing a "0" into this bit-field enables the chan- nel(n)transmit driver. n ote : in order to permit a system designed for redundancy to quickly shut-off a defective line card and turn-on the back-up line card, the XRT73L04B was designed such that either transmitter can quickly be turned-on or turned-off by toggling the txoff input pins. this approach is much quicker then setting the txoff_(n) bit-fields via the micro- processor serial interface. table 6 presents a truth table which relates the set- ting of the txoff external pin and bit-field for a chan- nel to the state of the transmitter. this table applies to all channels of the XRT73L04B. to control the state of all transmitters via the micro- processor serial interface, connect the txoff input pin to gnd. 4.5 t he t ransmit d rive m onitor f eatures the transmit drive monitor is used to monitor the line in the transmit direction for the occurrence of fault conditions such as a short circuit on the line, a defec- tive transmit drive in the XRT73L04B or another liu. activate the channel(n) transmit drive monitor by connecting the mtip_(n) pin to the ttip_(n) line through a 270 ohm resistor connected in series, and connecting the mring_(n) pin to the tring_(n) line through a 270 ohm resistor connected in series. such an approach is illustrated in figure 36. command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) reserved 1x x xx t able 6: t he r elationship b etween the t x off i nput p in , the t x off b it f ield and the s tate of the t ransmitter s tate of the t x off i nput p in s tate of the t x off b it f ield s tate of the t ransmitter low 0 on (transmitter is active) low 1 off (transmitter is tri-stated) high 0 off (transmitter is tri-stated) high 1 off (transmitter is tri-stated)
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 51 when the transmit drive monitor circuitry within a given line is connected to the line, as illustrated in figure 36, then it monitors the line for transitions. as long as the transmit drive monitor circuitry detects transitions on the line via the mtip_(n) and mring_(n) pins, then it keeps the dmo (drive moni- tor output) signal "low". if the transmit drive moni- tor circuit detects no transitions on the line for 128+ 32 txclk periods, then the dmo (drive monitor output) signal toggles "high". n ote : the transmit drive monitor circuit does not have to be used to operate the transmit section of the XRT73L04B. this is purely a diagnostic feature. 4.6 t he taos (t ransmit a ll o ne s) f eature the XRT73L04B can command any channel to trans- mit an all 1s" pattern onto the line by toggling a sin- gle input pin or by setting a single bit-field within one of the command registers to "1". n ote : when this feature is activated, the transmit section of the configured channel overwrites the terminal equip- ment data with this all 1s" pattern. a. operating in the hardware mode configure channel(n) to transmit an all 1s" pattern by toggling the taos_(n) input pin (pin 45, 46, 135 or 136) high". terminate the all 1s" pattern by tog- gling the taos_(n) input pin low". b. operating in the host mode configure channel(n) to transmit an all 1s" pattern by writing to command register cr1-(n) and setting the taos_(n) bit-field (bit d3) to "1". terminate the all 1s" pattern by writing to command register cr1-(n) and setting the taos_(n) bit-field (d3) to "0". 5.0 the microprocessor serial inter- face the on-chip command registers of XRT73L04B ds3/e3/sts-1 line interface unit ic are used to con- figure the XRT73L04B into a wide-variety of modes. this section discusses the following: 1. the description of the command registers. 2. a description on how to use the microprocessor serial interface. 5.1 d escription of the c ommand r egisters (repeated as table 7), lists the command registers, their addresses and their bit-formats. f igure 36. t he XRT73L04B employing the t ransmit d rive m onitor f eatures r1 = 31.6 w r2 = 31.6 w channel (n) txpos_(n) txneg_(n) txlineclk_(n) ttip_(n) tring_(n) tpdata_(n) tndata_(n) txclk_(n) only one channel shown 1:1 j1 bnc mtip_(n) mring_(n) r3 = 270 w r4 = 270 w command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) reserved 0 1xxx
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 52 t able 7: h exadecimal a ddresses and b it f ormats of XRT73L04B c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 c hannel 0 0x00 cr0-0 ro rlol_0 rlos_0 alos_0 dlos_0 dmo_0 0x01 cr1-0 r/w txoff_0 taos_0 txclkinv_0 txlev_0 reserved 0x02 cr2-0 r/w reserved reserved alosdis_0 dlosdis_0 reqen_0 0x03 cr3-0 r/w (sr/dr )_0 losmut_0 rxoff rxclk_0inv reserved 0x04 cr4-0 r/w reserved sts-1/ds3 _0 e3_0 llb_0 rlb_0 0x05 cr5-0 r/w reserved reserved reserved reserved reserved 0x06 cr6-0 r/w reserved reserved reserved reserved reserved 0x07 cr7-0 r/w reserved reserved reserved reserved reserved c hannel 1 0x08 cr0-1 ro rlol_1 rlos_1 alos_1 dlos_1 dmo_1 0x09 cr1-1 r/w txoff_1 taos_1 txclkinv_1 txlev_1 reserved 0x0a cr2-1 r/w reserved reserved alosdis_1 dlosdis_1 reqen_1 0x0b cr3-1 r/w sr/dr _1 losmut_1 rxoff rxclk_1inv reserved 0x0c cr4-1 r/w reserved sts-1/ds3 _1 e3_1 llb_1 rlb_1 0x0d cr5-1 r/w reserved reserved reserved reserved reserved 0x0e cr6-1 r/w reserved reserved reserved reserved reserved 0x0f cr7-1 r/w reserved reserved reserved reserved reserved c hannel 2 0x10 cr0-2 ro rlol_2 rlos_2 alos_2 dlos_2 dmo_2 0x11 cr1-2 r/w txoff_2 taos_2 txclkinv_2 txlev_2 reserved 0x12 cr2-2 r/w reserved reserved alosdis_2 dlosdis_2 reqen_2 0x13 cr3-2 r/w sr/dr _2 losmut_2 rxoff rxclk_2inv reserved 0x14 cr4-2 r/w reserved sts-1/ds3 _2 e3_2 llb_2 rlb_2 0x15 cr5-2 r/w reserved reserved reserved reserved reserved 0x16 cr6-2 r/w reserved reserved reserved reserved reserved 0x17 cr7-2 r/w reserved reserved reserved reserved reserved
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 53 address the register addresses are presented in the hexa- decimal format. type: the command registers are either read-only (ro) type of registers or read/write (r/w) type of regis- ters. each channel of the XRT73L04B has eight command registers, cr0-(n) through cr7-(n) where (n) = 0, 1, 2 or 3. the associated addresses for each channel are presented in , (repeated as table 7). n ote : the default value for each of the bit-fields within these register is "0". 5.2 d escription of b it -f ields for each c om - mand r egister 5.2.1 command register - cr0-(n) the bit-format and default values for command reg- ister cr0-(n) are listed below followed by the function of each of these bit-fields. bit d4 - rlol_(n) (receive loss of lock status - channel(n)) this read-only bit-field reflects the lock status of the channel(n) clock recovery phase-locked-loop this bit-field is set to 0 if the channel(n) clock re- covery pll is in lock with the incoming line signal. this bit-field is set to "1" if the clock recovery pll is out of lock with the incoming line signal. bit d3 - rlos_(n) (receive loss of signal status - channel(n)) this read-only bit-field indicates whether or not the channel(n) of the receiver is currently declaring an los (loss of signal) condition. this bit-field is set to "0" if channel(n) is not currently declaring the los condition. this bit-field is set to "1" if channel(n) is declaring an los condition. bit d2 - alos_(n) (analog loss of signal status - channel(n)) this read-only bit-field indicates whether or not the channel(n) analog los detector is currently declar- ing an los condition. this bit-field is set to "0" if the analog los detector within channel(n) is not currently declaring an los condition. this bit-field is set to "1" if the analog los detector is currently declaring an los condition. n ote : the purpose is to isolate the detector (e.g., either the analog los or the digital los detector) that is declar- ing the los condition. this feature may be useful for trou- bleshooting/debugging purposes bit d1 - dlos_(n) (digital loss of signal status - channel(n)) this read-only bit-field indicates whether or not the channel(n) digital los detector is currently declar- ing an los condition. this bit-field is set to "0" if the channel(n) digital los detector is not currently declaring an los condi- c hannel 3 0x18 cr0-3 ro rlol_3 rlos_3 alos_3 dlos_3 dmo_3 0x19 cr1-3 r/w txoff_3 taos_3 txclkinv_3 txlev_3 reserved 0x1a cr2-3 r/w reserved reserved alosdis_3 dlosdis_3 reqen_3 0x1b cr3-3 r/w sr/dr _3 losmut_3 rxoff rxclk_3inv reserved 0x1c cr4-3 r/w reserved sts-1/ds3 _3 e3_3 llb_3 rlb_3 0x1d cr5-3 r/w reserved reserved reserved reserved reserved 0x1e cr6-3 r/w reserved reserved reserved reserved reserved 0x1f cr7-3 r/w reserved reserved reserved reserved reserved t able 7: h exadecimal a ddresses and b it f ormats of XRT73L04B c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 command register cr0-(n) d4 d3 d2 d1 d0 rlol_(n) rlos_(n) alos_(n) dlos_(n) dmo_(n) 1 1111
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 54 tion. this bit-field is set to "1" if the channel(n) digital los detector is currently declaring an los condition. n ote : the purpose is to isolate the detector (e.g., either the analog los or the digital los detector) that is declar- ing the los condition. this feature may be useful for trou- bleshooting/debugging purposes. bit d0 - dmo_(n) (drive monitor output status - channel(n)) this read-only bit-field reflects the status of the dmo output pin. 5.2.2 command register cr1 the bit-format and default values for command reg- ister cr1-(n) are listed below followed by the function of each of these bit-fields.. bit d4 - txoff_(n) (transmitter off - channel(n)) this read/write bit-field is used to turn off the chan- nel(n) transmitter. writing a "1" to this bit field turns off the transmitter and tri-state the transmit output. writing a "0" to this bit-field turns on the transmitter. bit d3 - taos_(n) (transmit all ones - chan- nel(n)) this read/write bit-field is used to command the channel(n) transmitter to generate and transmit an all 1s pattern onto the line. writing a "1" to this bit-field commands the transmit- ter to transmit an all 1s pattern onto the line. writ- ing a "0" to this bit-field commands normal operation. bit d2 - txclkinv_(n) (transmit clock invert - channel(n)) this read/write bit-field is used to configure the transmitter to sample the signal at the tpdata and tndata pins on the rising edge or falling edge of tx- clk (the transmit line clock signal). writing a "1" to this bit-field configures the transmitter to sample the tpdata and tndata input pins on the rising edge of txclk. writing a 0" to this bit-field con- figures the transmitter to sample the tpdata and tndata input pins on the falling edge of txclk. bit d1 - txlev_(n) (transmit line build-out en- able/disable select - channel(n)) this read/write bit-field is used to enable or disable the channel(n) transmit line build-out circuit. setting this bit-field "high" disables the channel(n) line build-out circuit. in this mode, channel(n) out- puts partially-shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. setting this bit-field "low" enables the channel(n) line build-out circuit. in this mode, channel(n) out- puts shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. in order to comply with the isolated dsx-3/stsx-1 pulse template requiremnts per bellcore gr-499- core or gr-253-core: a. set this bit-field to "1" if the cable length between the cross-connect and the transmit output of chan- nel(n) is greater than 225 feet. b. set this bit-field to "0" if the cable length between the cross-connect and the transmit output of chan- nel(n) is less than 225 feet. this bit-field is active only if the XRT73L04B is config- ured to operate in the ds3 or sonet sts-1 modes. if the cable length is greater than 225 feet, set this bit- field to "1" in order to increase the amplitude of the transmit output signal. if the cable length is less than 225 feet, set this bit-field to "0". n ote : this option is only available when the XRT73L04B is operating in the ds3 or sts-1 mode. 5.2.3 command register cr2-(n) the bit-format and default values for command reg- ister cr2-(n) are listed below followed by the function of each of these bit fields. command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) reserved 00000 command register cr2-(n) d4 d3 d2 d1 d0 reserved reserved alosdis_(n) dlosdis_(n) reqen_(n) x0000
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 55 bit d4 - reserved bit d3 - reserved bit d2 - alosdis_(n) (analog los disable - channel(n)) this read/write bit-field is used to enable or disable the channel(n) analog los detector. writing a "0" to this bit-field enables the analog los detector. writing a "1" to this bit-field disables the analog los detector. n ote : if the analog los detector is disabled, then the rlos input pin is only asserted by the dlos (digital los detector). bit d1 - dlosdis_(n) (digital los disable - chan- nel(n)) this read/write bit-field to used to enable or disable the channel(n) digital los detector . writing a "0" to this bit-field enables the digital los detector. writing a "1" to this bit-field disables the digital los detector. n ote : if the digital los detector is disabled, then the rlos input pin is only asserted by the alos (analog los detector). bit d0 - reqen_(n) (receive equalization enable - channel(n)) this read/write bit-field is used to enable or disable the internal channel(n) receive equalizer. writing a "1" to this bit-field enables the internal equalizer. writing a "0" to this bit-field disables the internal equalizer. 5.2.4 command register cr3-(n) the bit-format and default values for command reg- ister cr3-(n) are listed below followed by the function of each of these bit fields. bit d4 - sr/dr (single-rail/dual-rail data output - channel(n))/(b3zs/hdb3 encoder/decoder-dis- able - channel(n)) this read/write bit-field is used to configure chan- nel(n) to output the received data from the remote terminal in a binary or dual-rail format and enable or disable the b3zs/hdb3 encoder and decoder blocks. writing a "1" to this bit-field enables the b3zs/hdb3 encoder and decoder blocks. writing a "0" to this bit- field disables the b3zs/hdb3 encoder and decoder blocks. n ote : this encoder/decoder performs hdb3 encoding/ decoding if the XRT73L04B is operating in the e3 mode. otherwise, it performs b3zs encoding/decoding. .writing a "1" to this bit-field also configures chan- nel(n) to output data to the terminal equipment in a binary (single-rail) format via the rpos_(n) output pin, rneg_(n) is grounded. writing a "0" to this bit- field configures channel(n) to output data to the ter- minal equipment in a dual-rail format via both the rpos_(n) and rneg_(n) output pins. bit d3 - losmut_(n) (recovered data muting, during los condition - channel(n)) this read/write bit-field is used to configure chan- nel(n) to not output any recovered data from the line while it is declaring an los condition. writing a "0" to this bit-field configures the chip to out- put recovered data even while the XRT73L04B is de- claring an los condition. writing a "1" to this bit-field configures the chip to not output the recovered data while an los condition is being declared. n ote : in this mode, rpos_(n) and rneg_(n) is set to "0", asynchronously. bit d2 - rxoff (receive section - shut off se- lect) this read/write bit-field is used to shut-off the re- ceive sections. the purpose is to conserve power consumption when this device is the back-up device in a redundancy system. writing a "1" into this bit-field shuts off the receive sections. writing a "0" into this bit-field turns on the receive sections. bit d1 - rxclk_(n)inv (invert rxclk_(n)) this read/write bit-field is used to configure the channel(n) receiver to output the recovered data on either the rising edge or the falling edge of the rxclk_(n) clock signal. writing a "0" to this bit-field configures the receiver to output the recovered data on the rising edge of the rxclk_(n) output signal. writing a "1" to this bit-field configures the receiver to output the recovered data on the falling edge of the rxclk_(n) output signal. bit d0 - reserved command register cr3-(n) d4 d3 d2 d1 d0 sr/dr _(n) losmut_(n) rxoff rxclk_(n)inv reserved 00000
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 56 this bit-field has no defined functionality command register cr4-(n) the bit-format and default values for command reg- ister cr4 are listed below followed by the function of each of these bit-fields. bit d4 - reserved this bit-field has no defined functionality bit d3 - sts-1/(ds3 _(n)) - channel(n) - mode se- lect this read/write bit field is used to configure chan- nel(n) to operate in either the sonet sts-1 mode or the ds3 mode. writing a "0" into this bit-field configures channel(n) to operate in the ds3 mode. writing a "1" into this bit- field configures channel(n) to operate in the sonet sts-1 mode. n ote : this bit-field is ignored if the e3_(n) bit-field (e.g., d2 within this command register) is set to "1". bit d2 - e3 mode select - channel(n) this read/write bit-field is used to configure chan- nel(n) to operate in the e3 mode. writing a "0" into this bit-field configures channel(n) to operate in either the ds3 or sonet sts-1 mode as specified by the setting of the ds3 bit-field within this command register. writing a "1" into this bit- field configures channel(n) to operate in the e3 mode. bit d1 - llb_(n) (local loop-back - channel(n)) this read/write bit-field along with rlb_(n) is used to configure channel(n) to operate in any one of a va- riety of loop-back modes. table 8 relates the contents of llb_(n) and rlb_(n) and the corresponding loop-back mode for chan- nel(n). bit d0 - rlb_(n) (remote loop-back - chan- nel(n)) this read/write bit-field, along with llb_(n), is used to configure channel(n) to operate in any one of a va- riety of loop-back modes. table 8 relates the contents of llb_(n) and rlb_(n) and the corresponding loop-back mode for chan- nel(n). 5.3 o perating the m icroprocessor s erial i nterface . the XRT73L04B serial interface is a simple four wire interface that is compatible with many of the micro- controllers available in the market. this interface consists of the following signals: ? cs - chip select (active low) ? sclk - serial clock ? sdi - serial data input ? sdo - serial data output using the microprocessor serial interface the following instructions for using the microproces- sor serial interface are best understood by referring to the diagram in figure 37 and the timing diagram in figure 38. in order to use the microprocessor serial interface, a clock signal must be first applied to the sclk input pin. then, initiate a read or write operation by as- serting the active-low chip select input pin cs . it is important to assert the cs pin (e.g., toggle it low") at least 5ns prior to the very first rising edge of the clock signal. once the cs input pin has been asserted, the type of operation and the target register address must now be specified. provide this information to the micro- processor serial interface by writing eight serial bits of data into the sdi input. command register cr4-(n) d4 d3 d2 d1 d0 reserved sts-1/ds3 _(n) e3_(n) llb_(n) rlb_(n) 00000 t able 8: c ontents of llb_(n) and rlb_(n) and the c orresponding l oop -b ack m ode for c hannel (n) llb _(n) rlb _(n) l oop -b ack m ode ( for c hannel (n) ) 0 0 none 1 0 analog loop-back mode (see section 4.1 for details) 1 1 digital loop-back mode (see section 4.2 for details) 0 1 remote loop-back mode (see section 4.3 for details)
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 57 n ote : each of these bits is clocked into the sdi input on the rising edge of sclk. bit 1 - r/w (read/write) bit this bit is clocked into the sdi input, on the first rising edge of sclk after cs has been asserted. this bit in- dicates whether the current operation is a read or write operation. a "1" in this bit specifies a read op- eration, a "0" in this bit specifies a write operation. bits 2 through 6: the five (5) bit address values (labeled a0, a1, a2 , a3 and a4) the next five rising edges of the sclk signal clocks in the 5-bit address value for this particular read or write operation. the address selects the command register in the XRT73L04B that the user is either reading data from or writing data to. the address bits must be supplied to the sdi input pin in ascending or- der with the lsb (least significant bit) first. bit 7: a5 must be set to "0", as shown in figure 37. bit 8 - a6 the value of a6 is a don't care. once these first 8 bits have been written into the mi- croprocessor serial interface, the subsequent action depends upon whether the current operation is a read or write operation. read operation once the last address bit (a4) has been clocked into the sdi input, the read operation proceeds through an idle period lasting two sclk periods. on the falling edge of sclk cycle #8 (see figure 37) the serial data output signal (sdo) becomes active. at this point, reading the data contents of the addressed com- mand register at address [a4, a3, a2, a1, a0] via the sdo output pin can begin. the microprocessor serial interface outputs this five bit data word (d0 through d4) in ascending order with the lsb first on the falling edges of the sclk pin. consequently, the data on the sdo output pin is sufficiently stable for reading by the microprocessor on the very next rising edge of the sclk pin. write operation once the last address bit (a4) has been clocked into the sdi input, the write operation proceeds through an idle period lasting two sclk periods. prior to the rising edge of sclk cycle # 9 (see figure 37). apply the desired eight bit data word to the sdi input pin via the microprocessor serial interface. the micropro- cessor serial interface latches the value on the sdi input pin on the rising edge of sclk. apply this word (d0 through d7) serially, in ascending order with the lsb first. simplified interface option the design of the circuitry connecting to the micro- processor serial interface can be simplified by tying both the sdo and sdi pins together and reading data from and/or writing data to this combined signal. this simplification is possible because only one of these signals are active at any given time. the inactive sig- nal is tri-stated. n otes : 1. a5 is always "0" 2. r/w = "1" for read operations 3. r/w = "0" for write operations 4. shaded box denotes a don't care value f igure 37. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 58 f igure 38. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 59 ordering information package dimensions p art #p ackage o perating temperature r ange XRT73L04Biv 144 pin lqfp 20 x 20 x 1.4mm -40c to +85c t hermal i nformation theta-j a = 24 c/w theta-j c = 5.5 c/w note: the control dimension is the millimeter column 144 lead quad flat pack (20 x 20 x 1.4 mm lqfp) rev. 1.00 a 2 a l c e 108 73 72 37 109 144 d d 1 d d 1 1 36 b a 1 a seating plane symbol min max min max a 0.055 0.063 1.4 1.6 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.858 0.874 21.8 22.2 d1 0.783 0.791 19.9 20.1 e l 0.018 0.03 0.45 0.75 a 0 o 7 o 0 o 7 o millimeters inches 0.020 bsc 0.50 bsc b 0.490 0.510 12.45 12.96
XRT73L04B 4 channel ds3/e3/sts-1 line interface unit rev. 1.0.1 60 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2003 exar corporation datasheet october 2003. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r ev #d ate c hanges m ade p1.0.0 may 2002 original 1.0.0 july 2003 final release. changed theta-ja and theta-jc. icc in electrical tables returned to 500ma max for the 4-channel device. changed tqfp to lqfp. 1.0.1 october 2003 changed the default register setting for losmut_(n) in cr3.

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